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w WM8953 low power stereo adc with pll and tdm interface wolfson microelectronics plc to receive regular email updates, sign up at http://www.wolfsonmicro.com/enews/ production data, january 2009, rev 4.0 copyright ? 2009 wolfson microelectronics plc description the WM8953 is a low power high performance stereo adc designed for mobile handsets and other portable devices. four single-ended or differential input connections are provided, with up to 60db of analogue gain in each input path. stereo 24- bit sigma-delta adcs provide hi-fi quality audio recording of microphones or line input. a programmable high pass filter is available in the adc path for removing dc offsets and suppressing wind and other low frequency noise. a low noise microphone bias with programmable current detect and short-circuit detect is provided. a flexible digital audio interface supports most commonly-used clocking schemes. the audio interface supports tdm and tristate outputs allow multiple devices to share the same interface. an integrated low power pll provides support for most commonly-used audio sample rates. the WM8953 is supplied in very small and thin 42-ball wcsp package, ideal for portable systems. features ? snr 94db (?a? weighted) ? thd -82db at 48khz, 3.3v ? full stereo microphone / line input interface ? low noise micbias ? low power consumption ? full analogue and digital volume control ? pll provides flexible clocking scheme ? 2-wire, 3-wire or 4-wire control ? sample rates: 8, 11.025, 12, 16, 22.05, 24, 32, 44.1, 48khz ? gpio functions available ? digital supply: 1.71v ? 3.6v ? analogue supply: 2.7v ? 3.6v ? w-csp package (3.226 x 3.44 x 0.7mm, 0.5mm pitch) applications ? multimedia phones ? general purpose low power audio adc
WM8953 production data w pd, january 2009, rev 4.0 2 table of contents description .......................................................................................................1 features.............................................................................................................1 applications .....................................................................................................1 table of contents .........................................................................................2 block diagram .................................................................................................3 pin configuration...........................................................................................4 ordering information ..................................................................................4 pin description ................................................................................................5 absolute maximum ratings.........................................................................6 recommended operating conditions .....................................................6 thermal performance .................................................................................7 electrical characteristics ......................................................................8 terminology........................................................................................................... 12 typical power consumption ....................................................................13 psrr performance.......................................................................................14 audio signal paths.......................................................................................15 signal timing requirements .....................................................................16 system clock timing............................................................................................ 16 audio interface timing ? master mode ......................................................... 17 audio interface timing ? slave mode ............................................................ 18 audio interface timing ? tdm mode ................................................................ 19 control interface timing ? 2-wire mode ..................................................... 20 control interface timing ? 3-wire mode ..................................................... 21 control interface timing ? 4-wire mode ..................................................... 22 internal power on reset circuit ..........................................................23 device description .......................................................................................25 introduction.......................................................................................................... 25 input signal path.................................................................................................. 26 analogue to digital converter (adc) .......................................................... 36 digital audio paths .............................................................................................. 39 thermal sensing ................................................................................................... 40 general purpose input/output ...................................................................... 41 digital audio interface...................................................................................... 56 digital audio interface control ................................................................... 63 clocking and sample rates .............................................................................. 67 control interface .............................................................................................. 75 power management ............................................................................................. 79 power domains...................................................................................................... 81 register map...................................................................................................82 register bits by address .................................................................................. 84 digital filter characteristics ...............................................................97 adc filter responses ......................................................................................... 97 adc high pass filter responses ..................................................................... 97 applications information .........................................................................98 recommended external components........................................................... 98 package dimensions ....................................................................................99 important notice ........................................................................................100 address:................................................................................................................. 100
production data WM8953 w pd, january 2009, rev 4.0 3 block diagram
WM8953 production data w pd, january 2009, rev 4.0 4 pin configuration ordering information order code temperature range package moisture sensitivity level peak soldering temperature WM8953ecs/rv -40 c to +85 c 42-ball w-csp (pb-free, tape and reel) msl3 260 c note: reel quantity = 3500
production data WM8953 w pd, january 2009, rev 4.0 5 pin description pin no name type description a2 micbias analogue output microphone bias d3 lin1 analogue input left channel single-ended mic input / left channel negative differential mic input c5 lin2 analogue input left channel line input / left channel positive differential mic input c6 lin3 / gpi7 analogue input / digital input left channel line input / left channel negative differential mic input / accessory or button detect input pin b6 lin4 analogue input left channel line input / left channel positive differential mic input / d4 rin1 analogue input right channel single-ended mic input / right channel negative differential mic input d6 rin2 analogue input right channel line input / right channel positive differential mic input d5 rin3 / gpi8 analogue input / digital input right channel line input / right channel negative differential mic input / accessory or button detect input pin e5 rin4 analogue input left channel line input / left channel positive differential mic input / f6 dcvdd supply digital core supply e6 dgnd supply digital ground (return path for both dcvdd and dbvdd) g6 dbvdd supply digital buffer (i/o) supply a6 avdd supply analogue supply a3, b1, b3 agnd supply analogue ground (return path for avdd) f5 mclk digital input master clock g5 bclk digital input / output audio interface bit clock e4 adclrc digital input / output audio interface adc left / right clock f4 adcdat digital output adc digital audio data e2 mode digital input selects 2-wire or 3/4 -wire control f2 csb / addr digital input 3/4 -wire chip select or 2-wire address select f1 sclk digital input control interface clock input e3 sdin digital input / output control interface data input / 2-wire acknowledge output c3 vmid analogue output midrail voltage decoupling capacitor g2 gpio3 digital input / output gpio pin g3 gpio4 digital input / output gpio pin g1 gpio5 digital input / output gpio pin a1, a4, a5, b2, b4, b5, c1, c2, c4, d1, d2, e1, f3, g4 dnc do not connect
WM8953 production data w pd, january 2009, rev 4.0 6 absolute maximum ratings absolute maximum ratings are stress ratings only. permanent damage to the device may be caused by continuously operating at or beyond these limits. device functional operating limits and guaranteed performance specifications are given under electrical characteristics at the test conditions specified. esd sensitive device. this device is manufactured on a cmos process. it is therefore generically susceptible to damage from excessive static voltages. proper esd precautions must be taken during handling and storage of this device. wolfson tests its package types according to ipc/jedec j-std-020b for moisture sensitivity to determine acceptable storage conditions prior to surface mount assembly. these levels are: msl1 = unlimited floor life at <30 c / 85% relative humidity. not normally stored in moisture barrier bag. msl2 = out of bag storage for 1 year at <30 c / 60% relative humidity. supplied in moisture barrier bag. msl3 = out of bag storage for 168 hours at <30 c / 60% relative humidity. supplied in moisture barrier bag. the moisture sensitivity level for each package type is specified in ordering information. condition min max supply voltages -0.3v +4.5v voltage range digital inputs dgnd -0.3v dbvdd +0.3v voltage range analogue inputs agnd -0.3v avdd +0.3v operating temperature range, t a -40oc +85oc junction temperature, t jmax -40oc +150oc storage temperature after soldering -65oc +150oc recommended operating conditions parameter symbol min typ max unit digital supply range (core) dcvdd 1.71 3.6 v digital supply range (buffer) dbvdd 1.71 3.6 v analogue supply range avdd 2.7 3.6 v ground dgnd, agnd 0 v notes 1. analogue and digital grounds must always be within 0.3v of each other. 2. all digital and analogue supplies are completely independent from each other (i.e. not internally connected). 3. dcvdd must be less than or equal to avdd. 4. dcvdd must be less than or equal to dbvdd.
production data WM8953 w pd, january 2009, rev 4.0 7 thermal performance thermal analysis should be performed in the intended application to prevent the WM8953 from exceeding maximum junction temperature. several contributing factors affect thermal performance most notably the physical properties of the mechanical enclosure, location of the device on the pcb in relation to surrounding components and the number of pcb layers. connecting the gnd balls through thermal vias and into a large ground plane will aid heat extraction. three main heat transfer paths exist to surrounding air as illustrated below in figure 1: - package top to air (radiation). - package bottom to pcb (radiation). - package balls to pcb (conduction). figure 1 heat transfer paths the temperature rise t r is given by t r = p d * ? ja - p d is the power dissipated in the device. - ? ja is the thermal resistance from the junction of the die to the ambient temperature and is therefore a measure of heat transfer from the die to surrounding air. ? ja is determined with reference to jedec standard jesd51-9. the junction temperature t j is given by t j = t a +t r , where t a is the ambient temperature. parameter symbol min typ max unit operating temperature range t a -40 85 c operating junction temperature t j -40 100 c thermal resistance ? ja 43 c/w
WM8953 production data w pd, january 2009, rev 4.0 8 electrical characteristics test conditions dcvdd = 1.8v, dbvdd = 3.3v, avdd = 3.3v, t a = +25 o c, 1khz signal, fs = 48khz, pga gain = 0db, 24-bit audio data unless otherwise stated. parameter test conditions min typ max unit analogue input pin maximum signal levels (lin1, lin2, lin3, lin4, rin1, rin2, rin3, rin4) single-ended pga input on lin1, lin3, rin1 or rin3, output to inmixl or inmixr 1.0 0 vrms dbv maximum full-scale pga input signal level note 1; note 2; note 3 differential pga input on lin1/lin2, lin3/lin4, rin1/rin2 or rin3/rin4, output to inmixl or inmixr 1.0 0 vrms dbv maximum full-scale line input signal level note 1; note 2; note 3 line input on lin2, lin4, rin2 or rin4 to inmixl or inmixr 1.0 0 vrms dbv notes 1. maximum full scale signal changes in proportion to avdd (avdd/3.3). 2. when mixing input pga outputs and line inputs, the total signal must not exceed 1vrms (0dbv). 3. a 1.0vrms differential signal equates to 0.5vrms/-6dbv per input.
production data WM8953 w pd, january 2009, rev 4.0 9 test conditions dcvdd = 1.8v, dbvdd = 3.3v, avdd = 3.3v, t a = +25 o c, 1khz signal, fs = 48khz, pga gain = 0db, 24-bit audio data unless otherwise stated. parameter test conditions min typ max unit analogue input pin impedances (lin1, lin2, lin3, lin4, rin1, rin2, rin3, rin4) lin1, lin3, rin1 or rin3 (pga gain = -16.5db) 57 k ? lin1, lin3, rin1 or rin3 (pga gain = 0db) 33 k ? lin1, lin3, rin1 or rin3 (pga gain = +30db) 2 k ? pga input resistance note: this will be seen in parallel with the resistance of other enabled input paths from the same pin lin2, lin4, rin2 or rin4 (constant for all gains) 65 k ? lin2 or rin2 to inmixl or inmixr (-12db) 60 k ? lin2 or rin2 to inmixl or inmixr (0db) 15 k ? line input resistance note: this will be seen in parallel with the resistance of other enabled input paths from the same pin lin2 or rin2 to inmixl or inmixr (+6db) 7.5 k ? input capacitance all analogue input pins 10 pf test conditions dcvdd = 1.8v, dbvdd = 3.3v, avdd = 3.3v, t a = +25 o c, 1khz signal, fs = 48khz, pga gain = 0db, 24-bit audio data unless otherwise stated. parameter test conditions min typ max unit input programmable gain amplifiers (pgas) lin12, lin34, rin12 and rin34 minimum programmable gain -16.5 db maximum programmable gain 30 db programmable gain step size guaranteed monotonic 1.5 db mute attenuation inputs disconnected 90 db single pga in differential mode, gain = +30db 60 single pga in differential mode, gain = 0db 50 common mode rejection ratio (1khz input) single pga in differential mode, gain = -16.5db 50 db input mixers inmixl and inmixr minimum programmable gain pga outputs to inmixl and inmixr 0 db maximum programmable gain pga outputs to inmixl and inmixr +30 db programmable gain step size pga outputs to inmixl and inmixr 30 db minimum programmable gain line inputs to inmixl and inmixr -12 db maximum programmable gain line inputs to inmixl and inmixr +6 db programmable gain step size line inputs to inmixl and inmixr 3 db mute attenuation 95 db
WM8953 production data w pd, january 2009, rev 4.0 10 test conditions dcvdd = 1.8v, dbvdd = 3.3v, avdd = 3.3v, t a = +25 o c, 1khz signal, fs = 48khz, pga gain = 0db, 24-bit audio data unless otherwise stated. parameter test conditions min typ max unit adc input path performance snr (a-weighted) 84 94 db thd (-1dbfs input) -84 -75 db thd+n (-1dbfs input) -82 -73 db crosstalk (l/r) -100 db avdd psrr (217hz) 45 db dcvdd psrr (217hz) line inputs to adc via inmixl and inmixr, avdd = 3.3v 80 db snr (a-weighted) 93 db thd (-1dbfs input) -78 db thd+n (-1dbfs input) line inputs to adc via inmixl and inmixr, avdd = 2.7v -76 db snr (a-weighted) 84 94 db thd (-1dbfs input) -84 -75 db thd+n (-1dbfs input) -82 -73 db crosstalk (l/r) -100 db avdd psrr (217hz) input pgas to adc via inmixl or inmixr, avdd = 3.3v 45 db snr (a-weighted) 92 db thd (-1dbfs input) -78 db thd+n (-1dbfs input) input pgas to adc via inmixl or inmixr, avdd = 2.7v -76 db
production data WM8953 w pd, january 2009, rev 4.0 11 test conditions dcvdd = 1.8v, dbvdd = 3.3v, avdd = 3.3v, t a = +25 o c, 1khz signal, fs = 48khz, pga gain = 0db, 24-bit audio data unless otherwise stated. parameter test conditions min typ max unit analogue reference levels vmid midrail reference voltage -3% avdd/2 +3% v microphone bias 3ma load current mbsel=0 -5% 0.9 avdd +5% v bias voltage 3ma load current mbsel=1 -5% 0.65 avdd +5% v bias current source 3 ma output noise density 1khz to 20khz 100 nv/ hz avdd psrr (217hz) 100mv pk-pk @217hz on avdd 45 db digital input / output input high level 0.7 dbvdd v input low level 0.3 dbvdd v note that digital input pins should not be left unconnected / floating. internal pull-up/pull-down resistors may be enabled on gpio3, gpio4 and gpio5 if required. output high level i ol =1ma 0.9 dbvdd v output low level i oh =-1ma 0.1 dbvdd v input capacitance 10 pf input leakage -0.9 0.9 ua pll prescale = 0b 7.7 18 mhz input frequency prescale = 1b 14.4 36 mhz lock time 200 us gpio sysclk=mclk; opclkdiv=0000 35 65 % sysclk=mclk; opclkdiv=1000 45 55 % sysclk=pll output; opclkdiv=0000 45 55 % clock output duty cycle (integer opclkdiv) sysclk=pll output; opclkdiv=1000 45 55 % sysclk=mclk; opclkdiv=0100 33 66 % clock output duty cycle (non-integer opclkdiv) sysclk=pll output; opclkdiv=0100 33 66 % input de-bounced 2 21 / f sysclk 2 22 / f sysclk s input de-bounced toclksel=1 2 19 / f sysclk 2 20 / f sysclk s interrupt response time for accessory / button detect input not de-bounced 0 s
WM8953 production data w pd, january 2009, rev 4.0 12 terminology 1. signal-to-noise ratio (db) ? snr is a measure of the difference in level between the maximum theoretical full scale output signal and the output with no input signal applied. 2. total harmonic distortion (db) ? thd is the level of the rms value of the sum of harmonic distortion products relative to the amplitude of the measured output signal. 3. total harmonic distortion plus noise (db) ? thd+n is the level of the rms value of the sum of harmonic distortion products plus noise in the specified bandwidth relative to the amplitude of the measured output signal. 4. crosstalk (l/r) (db) ? left-to-right and right-to-left channel crosstalk is the measured signal level in the idle channel at the test signal frequency relative to the signal level at the output of the active channel. the active channel is configured and supplied with an appropriate input signal to drive a full scale output, with signal measured at the output of the associated idle channel. for example, measured signal level on the output of the idle right channel (rin2 to adcr) with a full scale signal level at the output of the active left channel (lin1 to adcl). 5. multi-path channel separation (db) ? is the measured signal level in the idle path at the test signal frequency relative to the signal level at the output of the active path. the active path is configured and supplied with an appropriate input signal to drive a full scale output, with signal measured at the output of the specified idle path. 6. all performance measurements carried out with 20khz low pass filter, and where noted an a-weighted filter. failure to use such a filter will result in higher thd and lower snr readings than are found in the electrical characteristics. the low pass filter removes out of band noise; although it is not audible it may affect dynamic specification values. 7. mute attenuation ? this is a measure of the difference in level between the full scale output signal and the output with mute applied.
production data WM8953 w pd, january 2009, rev 4.0 13 typical power consumption a vdd dbvdd dcvdd iavdd idbvdd idcvdd total power (v) (v) (v) (ma) (ma) (ma) (mw) 2.7 1.8 1.8 0.028 0.000 0.000 0.075 3.0 2.5 2.5 0.029 0.000 0.000 0.087 3.3 3.3 3.3 0.030 0.000 0.000 0.099 3.6 3.6 3.6 0.031 0.000 0.000 0.114 2.7 1.8 1.8 0.008 0.000 0.000 0.020 3.0 2.5 2.5 0.008 0.000 0.000 0.024 3.3 3.3 3.3 0.009 0.000 0.000 0.029 3.6 3.6 3.6 0.009 0.000 0.000 0.035 2.7 1.8 1.8 0.087 0.004 0.459 1.068 3.0 2.5 2.5 0.096 0.008 0.694 2.044 3.3 3.3 3.3 0.106 0.014 1.025 3.780 3.6 3.6 3.6 0.117 0.017 1.162 4.667 2.7 1.8 1.8 5.272 0.023 2.285 18.389 3.0 2.5 2.5 5.603 0.039 3.317 25.199 3.3 3.3 3.3 5.927 0.060 4.728 35.358 3.6 3.6 3.6 6.261 0.063 5.295 41.830 2.7 1.8 1.8 5.125 0.017 0.758 15.233 3.0 2.5 2.5 5.434 0.027 1.123 19.177 3.3 3.3 3.3 5.738 0.061 1.634 24.528 3.6 3.6 3.6 6.053 0.062 1.841 28.642 with clocks fs=44.1khz fs=8khz stereo line record (l/rin2 to inmixl/r bypassing pga) stereo line record (l/rin2 to inmixl/r bypassing pga) mode other settings adc reco rd standby/sleep off (default state at power-up) off (thermal sensor disabled) sleep (vmid enabled, thermal sensor anabled) no clocks no clocks notes: 1. all figures are quoted at t a = +25oc 2. all figures are quoted as quiescent current unless otherwise stated.
WM8953 production data w pd, january 2009, rev 4.0 14 psrr performance dcvdd ? line-in to adc avdd ? line-in to adc psrr - dcvdd line-in to adc 0 10 20 30 40 50 60 70 80 90 0.1 1 10 100 frequency (khz) psrr (db) in2-inmix-adc - 3.3v dcvdd in2-inmix-adc - 2.0v dcvdd psrr - avdd line-in to adc 0 10 20 30 40 50 60 70 80 90 0.1 1 10 100 frequency (khz) psrr (db) in2-inmix-adc - 3.3v avdd in1pga-inmix-adc - 3.3v avdd avdd ? micbias psrr - avdd micbias 0 10 20 30 40 50 60 70 80 90 0.1 1 10 100 frequency (khz) psrr (db) micbias - mbsel = 0 micbias - mbsel = 1 note: all figures based on 100mvp-p injected on the supply at the relevant test frequency.
production data WM8953 w pd, january 2009, rev 4.0 15 audio signal paths
WM8953 production data w pd, january 2009, rev 4.0 16 signal timing requirements system clock timing figure 2 system clock timing requirements test conditions dcvdd=1.8v, dbvdd=avdd=3.3v, dgnd=agnd=0v, t a = +25 o c parameter symbol conditions min typ max unit system clock timing information mclk cycle time t mclky 33.33 ns mclk duty cycle = t mclkh /t mclkl 60:40 40:60 mclk t mclkl t mclkh t mclky
production data WM8953 w pd, january 2009, rev 4.0 17 audio interface timing ? master mode figure 3 digital audio data timing - master mode (see control interface) test conditions dcvdd=1.8v, dbvdd=avdd=3.3v, dgnd=agnd=0v, t a =+25 o c, master mode, fs=48khz, mclk=256fs, 24-bit data, unless otherwise stated. parameter symbol min typ max unit audio data timing information adclrc propagation delay from bclk falling edge t dl 20 ns adcdat propagation delay from bclk falling edge t dda 20 ns
WM8953 production data w pd, january 2009, rev 4.0 18 audio interface timing ? slave mode figure 4 digital audio data timing ? slave mode test conditions dcvdd=1.8v, dbvdd=avdd=3.3v, dgnd=agnd=0v, t a =+25 o c, slave mode, fs=48khz, mclk=256fs, 24-bit data, unless otherwise stated. parameter symbol min typ max unit audio data input timing information bclk cycle time t bcy 50 ns bclk pulse width high t bch 20 ns bclk pulse width low t bcl 20 ns adclrc set-up time to bclk rising edge t lrsu 20 ns adclrc hold time from rising edge t lrh 10 ns adcdat propagation delay from bclk falling edge t dd 20 ns note: bclk period should always be greater than or equal to mclk period.
production data WM8953 w pd, january 2009, rev 4.0 19 audio interface timing ? tdm mode in tdm mode, it is important that two adc devices to not attempt to drive the adcdat pin simultaneously. the timing of the WM8953 adcdat tri-stating at the start and end of the data transmission is described in figure 5 and the table below. figure 5 digital audio data timing - tdm mode test conditions avdd=3.3v, dgnd=agnd=0v, t a =+25 o c, master mode, fs=48khz, mclk=256fs, 24-bit data, unless otherwise stated. parameter conditions min typ max unit audio data timing information dcvdd = dbvdd = 3.6v 5 ns adcdat setup time from bclk falling edge dcvdd = dbvdd = 1.71v 15 ns dcvdd = dbvdd = 3.6v 5 ns adcdat release time from bclk falling edge dcvdd = dbvdd = 1.71v 15 ns
WM8953 production data w pd, january 2009, rev 4.0 20 control interface timing ? 2-wire mode 2-wire mode is selected by connecting the mode pin low. sdin sclk t 3 t 1 t 6 t 2 t 7 t 5 t 4 t 3 t 8 t 9 figure 6 control interface timing ? 2-wire serial control mode test conditions dcvdd=1.8v, dbvdd=avdd=3.3v, dgnd=agnd=0v, t a =+25 o c, slave mode, fs=48khz, mclk = 256fs, 24-bit data, unless otherwise stated. parameter symbol min typ max unit program register input information sclk frequency 526 khz sclk low pulse-width t 1 1.3 us sclk high pulse-width t 2 600 ns hold time (start condition) t 3 600 ns setup time (start condition) t 4 600 ns data setup time t 5 100 ns sdin, sclk rise time t 6 300 ns sdin, sclk fall time t 7 300 ns setup time (stop condition) t 8 600 ns data hold time t 9 900 ns pulse width of spikes that will be suppressed t ps 0 5 ns
production data WM8953 w pd, january 2009, rev 4.0 21 control interface timing ? 3-wire mode 3-wire mode is selected by connecting the mode pin high. figure 7 control interface timing ? 3-wire serial control mode (write cycle) csb sclk sdout t dl lsb figure 8 control interface timing ? 3-wire serial control mode (read cycle) test conditions dcvdd=1.8v, dbvdd=avdd=3.3v, dgnd=agnd=0v, t a =+25 o c, slave mode, fs=48khz, mclk=256fs, 24-bit data, unless otherwise stated. parameter symbol min typ max unit program register input information csb falling edge to sclk rising edge t csu 40 ns sclk falling edge to csb rising edge t cho 40 ns sclk pulse cycle time t scy 200 ns sclk pulse width low t scl 80 ns sclk pulse width high t sch 80 ns sdin to sclk set-up time t dsu 40 ns sdin to sclk hold time t dho 10 ns pulse width of spikes that will be suppressed t ps 0 5 ns sclk falling edge to sdout transition t dl 40 ns
WM8953 production data w pd, january 2009, rev 4.0 22 control interface timing ? 4-wire mode 4-wire mode supports readback via sdout which is available as a gpio pin function. figure 9 control interface timing ? 4-wire serial control mode (write cycle) csb sclk sdout t dl lsb figure 10 control interface timing ? 4-wire serial control mode (read cycle) test conditions dcvdd=1.8v, dbvdd=avdd=3.3v, dgnd=agnd=0v, t a =+25 o c, slave mode, fs=48khz, mclk=256fs, 24-bit data, unless otherwise stated. parameter symbol min typ max unit program register input information sclk rising edge to csb falling edge t csu 40 ns sclk falling edge to csb rising edge t cho 40 ns sclk pulse cycle time t scy 200 ns sclk pulse width low t scl 80 ns sclk pulse width high t sch 80 ns sdin to sclk set-up time t dsu 40 ns sdin to sclk hold time t dho 10 ns sdout propagation delay from sclk rising edge t dl 10 ns pulse width of spikes that will be suppressed t ps 0 5 ns sclk falling edge to sdout transition t dl 40 ns
production data WM8953 w pd, january 2009, rev 4.0 23 internal power on reset circuit figure 11 internal power on reset circuit schematic the WM8953 includes an internal power-on-reset circuit, as shown in figure 11, which is used to reset the digital logic into a default state after power up. the por circuit is powered from avdd and monitors dcvdd. it asserts porb low if avdd or dcvdd is below a minimum threshold. figure 12 typical power up sequence where avdd is powered before dcvdd figure 12 shows a typical power-up sequence where avdd comes up first. when avdd goes above the minimum threshold, v pora , there is enough voltage for the circuit to guarantee porb is asserted low and the chip is held in reset. in this condition, all writes to the control interface are ignored. now avdd is at full supply level. next dcvdd rises to v pord_on and porb is released high and all registers are in their default state and writes to the control interface may take place. on power down, where avdd falls first, porb is asserted low whenever avdd drops below the minimum threshold v pora_off .
WM8953 production data w pd, january 2009, rev 4.0 24 figure 13 typical power up sequence where dcvdd is powered before avdd figure 13 shows a typical power-up sequence where dcvdd comes up first. first it is assumed that dcvdd is already up to specified operating voltage. when avdd goes above the minimum threshold, v pora , there is enough voltage for the circuit to guarantee porb is asserted low and the chip is held in reset. in this condition, all writes to the control interface are ignored. when avdd rises to v pora_on , porb is released high and all registers are in their default state and writes to the control interface may take place. on power down, where dcvdd falls first, porb is asserted low whenever dcvdd drops below the minimum threshold v pord_off . symbol min typ max unit vpora 0.6 v vpora_on 1.52 v vpora_off 1.5 v vpord_on 0.92 v vpord_off 0.9 v table 1 typical por operation (typical values, not tested) notes: 1. if avdd and dcvdd suffer a brown-out (i.e. drop below the minimum recommended operating level but do not go below v pora_off or v pord_off ) then the chip will not reset and will resume normal operation when the voltage is back to the recommended level again. 2. the chip will enter reset at power down when avdd or dcvdd falls below v pora_off or v pord_off . this may be important if the supply is turned on and off frequently by a power management system. 3. the minimum t por period is maintained even if dcvdd and avdd have zero rise time. this specification is guaranteed by design rather than test.
production data WM8953 w pd, january 2009, rev 4.0 25 device description introduction the WM8953 is a low power, high quality audio adc designed to interface with a wide range of processors and analogue components. a high level of mixed-signal integration in a very small 3.226x3.44mm footprint makes it ideal for portable applications such as mobile phones. eight highly flexible analogue inputs allow interfacing to up to four microphone inputs plus multiple stereo or mono line inputs (single-ended or differential). the stereo adcs are of hi-fi quality using a 24-bit, low-order oversampling architecture to deliver optimum performance. a flexible clocking arrangement supports a wide variety of clock inputs and sample rates; the integrated ultra-low power pll provides additional flexibility. a high pass filter is available in the adc path for removing dc offsets and suppressing low frequency noise such as mechanical vibration and wind noise. the WM8953 has a highly flexible digital audio interface, supporting a number of protocols, including i 2 s, dsp, msb-first left/right justified, and can operate in master or slave modes. pcm operation is supported in the dsp mode. a-law and -law companding are also supported. time division multiplexing (tdm) is available to allow multiple devices to stream data simultaneously on the same bus, saving space and power. the sysclk (system clock) provides clocking for the adcs, dsp core and the digital audio interface. sysclk can be derived directly from the mclk pin or via an integrated pll, providing flexibility to support a wide range of clocking schemes. all mclk frequencies typically used in portable systems are supported for sample rates between 8khz and 48khz. to allow full software control over all its features, the WM8953 uses a standard 2-wire or 3/4-wire control interface with readback of key registers supported. it is fully compatible and an ideal partner for a wide range of industry standard microprocessors, controllers and dsps. unused circuitry can be disabled via software to save power, while low leakage currents extend standby and off time in portable battery-powered applications. the device address can be selected using the csb/addr pin. versatile gpio functionality is provided, with support for up to five button/accessory detect inputs with interrupt and status readback and flexible de-bouncing options, clock output, and logic '1' / logic '0' for control of additional external circuitry.
WM8953 production data w pd, january 2009, rev 4.0 26 input signal path the WM8953 has eight highly flexible analogue input channels, configurable in many combinations of the following: 1. up to four pseudo-differential or single-ended microphone inputs 2. up to eight mono line inputs or 4 stereo line inputs the input paths are mixed together as illustrated in figure 14. figure 14 control registers for input signal path microphone inputs up to four microphones can be connected to the WM8953, either in single-ended or pseudo- differential mode. a low noise microphone bias is fully integrated to reduce the need for external components. in single-ended microphone input configuration, the microphone signal is connected to the inverting input of the pga (lin1, lin3, rin1 or rin3). the non-inverting input of the pgas should be internally connected to vmid in this configuration. this is enabled via the input pga configuration register settings. in this configuration, lin2, lin4, rin2 or rin4 may be free to be used as line inputs. in pseudo-differential microphone input configuration, the non-inverted microphone signal is connected to the non-inverting input of the pga (lin2, lin4, rin2 or rin4) and the inverted (or noisy ground) signal is connected to the inverting input (lin1, lin3, rin1 or rin3). any pga input pin that is used in either microphone configuration should not be enabled as a line input path at the same time.
production data WM8953 w pd, january 2009, rev 4.0 27 the gain of the input pgas is controlled via register settings. note that the input impedance of lin1, lin3, rin1 and rin3 changes with the input pga gain setting, as described under ?electrical characteristics?. (note this does not apply to input paths which bypass the input pga.) the input impedance of lin2, lin4, rin2 and rin4 does not change with input pga gain. the inverting and non-inverting inputs are therefore not matched and the differential configuration is not fully differential. figure 15 single-ended microphone input figure 16 differential microphone input line inputs all eight analogue input pins may be configured as line inputs with up to six single-ended inputs available, and up to four pseudo differential inputs. lin1, lin3, rin1 and rin3 can operate as single-ended line inputs to the input pgas to provide high gain if required for small input signals. in this configuration the non-inverting input of the pgas should be internally connected to vmid. lin2 and rin2 can operate as line inputs to the input pgas lin12 and rin12 or directly to the input mixers. direct routing to the mixers minimises power consumption by reducing the number of active amplifiers in the signal path. lin4 and rin4 should only be used as part of a differential line input with lin3 and lin4. up to four differential line inputs can be connected to lin1+lin2, lin3+lin4, rin1+rin2 and rin3+rin4. figure 17 lin1, rin1, lin3 or rin3 as line inputs figure 18 lin2 or rin2 as line inputs figure 19 differential line inputs
WM8953 production data w pd, january 2009, rev 4.0 28 input pga enable the input pgas are enabled using register bits lin12_ena, lin34_ena, rin12_ena and rin34_ena as described in table 2. register address bit label default description 7 lin34_ena (rw) 0b lin34 input pga enable 0 = disabled 1 = enabled 6 lin12_ena (rw) 0b lin12 input pga enable 0 = disabled 1 = enabled 5 rin34_ena (rw) 0b rin34 input pga enable 0 = disabled 1 = enabled r2 (02h) 4 rin12_ena (rw) 0b rin12 input pga enable 0 = disabled 1 = enabled table 2 input pga enable reference voltages the analogue circuits in the WM8953 are referenced to vmid (avdd/2). this voltage is generated from avdd via a programmable resistor chain as shown in the audio signal paths diagram on page 15. together with the external decoupling capacitor on vmid, the programmable resistor chain results in a slow, normal or fast charging characteristic on vmid. the vmid reference is controlled by vmid_mode[1:0]. the analogue circuits in the WM8953 require a bias current. the bias current is enabled by setting vref_ena. note that the bias current source requires vmid to be enabled also. register address bit label default description 2:1 vmid_mode [1:0] (rw) 00b vmid divider enable and select 00 = vmid disabled (for off mode) 01 = 2 x 50k ? divider (normal mode) 10 = 2 x 250k ? divider (standby mode) 11 = 2 x 5k ? divider (for fast start-up) r1 (01h) 0 vref_ena (rw) 0b vref enable (bias for all analogue functions) 0 = vref bias disabled 1 = vref bias enabled table 3 reference voltages
production data WM8953 w pd, january 2009, rev 4.0 29 microphone bias control the micbias output provides a low noise reference voltage suitable for biasing electret type microphones via an external resistor. refer to the applications information section for recommended external components. the micbias voltage can be enabled or disabled using the micbias_ena control bit and the voltage can be selected using the mbsel register bit as detailed in table 4. register address bit label default description r1 (01h) 4 micbias_ena (rw) 0b microphone bias 0 = off (high impedance output) 1 = on r58 (3ah) 0 mbsel 0b microphone bias voltage control 0 = 0.9 * avdd 1 = 0.65 * avdd table 4 microphone bias control note that the maximum source current capability for micbias is 3ma. the external biasing resistance must be large enough to limit the micbias current to 3ma. microphone current detect a micbias current detect function allows detection of accessories such as headset microphones. when the micbias load current exceeds one of two programmable thresholds, (e.g. short circuit current or normal operating current), an interrupt or gpio output can be generated. the current detection circuit is enabled by the mcd bit; the current thresholds are selected by the mcdthr and mcdscth register fields as described in table 24- see ?general purpose input/output? for a full description of these fields. disabled input control after start-up, it may be desirable to disable an input stage, in order to reduce power consumption on an unused pga or input mixer. in order to avoid audible pops caused by a disabling any part of the input circuits, the WM8953 can maintain the input at vmid even when the pga or input mixer is disabled. this is achieved by connecting a buffered vmid reference to the input. the buffered vmid is enabled by setting bufioen. when bufioen is enabled, the WM8953 maintains the charge on the input capacitors connected to any disabled input amplifier. this suppresses the audible artefacts that would otherwise arise when an input amplifier is disabled or enabled. in some applications, a pop generated at an input stage can be entirely suppressed by correctly managing the output stages (eg. using the adc mute). however, it may be desirable to use the buffered vmid feature in order to eliminate the input pga start-up delay (the input capacitor charging time) in addition to suppressing any mute/un-mute pops. in applications where frequent enabling and configuration of signal paths is used, it is recommended to enable bufioen at all times. register address bit label default description r57 (39h) anti-pop 3 bufioen 0b enables the buffered vmid reference at disabled inputs 0 = disabled 1 = enabled table 5 disabled input/output control
WM8953 production data w pd, january 2009, rev 4.0 30 input pga configuration each of the four input pgas can be configured in single-ended or pseudo-differential mode. single-ended microphone operation of an input pga is selected by connecting the input source to the inverting pga input. the non-inverting pga input must be connected to vmid by setting the appropriate register bits. for pseudo-differential microphone operation, the inverting and non-inverting pga inputs are both connected to the input source and not to vmid. for any line input or other connection not using the input pga, the appropriate pga input should be disconnected from the external pin and connected to vmid. register bits lmn1, lmp2, lmn3, lmp4, rmn1, rmp2, rmn3 and rmp4 control connection of the pga inputs to the device pins as shown in table 6. the maximum available attenuation on any of these input paths is achieved using these bits to disable the input path to the applicable pga. register address bit label default description 7 lmp4 0b lin34 pga non-inverting input select 0 = lin4 not connected to pga 1 = lin4 connected to pga 6 lmn3 0b lin34 pga inverting input select 0 = lin3 not connected to pga 1 = lin3 connected to pga 5 lmp2 0b lin12 pga non-inverting input select 0 = lin2 not connected to pga 1 = lin2 connected to pga 4 lmn1 0b lin12 pga inverting input select 0 = lin1 not connected to pga 1 = lin1 connected to pga 3 rmp4 0b rin34 pga non-inverting input select 0 = rin4 not connected to pga 1 = rin4 connected to pga 2 rmn3 0b rin34 pga inverting input select 0 = rin3 not connected to pga 1 = rin3 connected to pga 1 rmp2 0b rin12 pga non-inverting input select 0 = rin2 not connected to pga 1 = rin2 connected to pga r40 (28h) 0 rmn1 0b rin12 pga inverting input select 0 = rin1 not connected to pga 1 = rin1 connected to pga table 6 input pga configuration
production data WM8953 w pd, january 2009, rev 4.0 31 input pga volume control each of the four input pgas has an independently controlled gain range of -16.5db to +30db in 1.5db steps. the gains on the inverting and non-inverting inputs to the pgas are always equal. each input pga can be independently muted using the pga mute bits as described in table 7, with specified mute attenuation achieved by simultaneously disconnecting the corresponding inputs described in table 6. to prevent "zipper noise", a zero-cross function is provided, so that when enabled, volume updates will not take place until a zero-crossing is detected. in the event of a long period without zero- crossings, a timeout function is available. when this function is enabled (using the toclk_ena register bit), the volume will update after the timeout period if no earlier zero-cross has occurred. the timeout period is set by toclk_rate. see ?clocking and sample rates? for more information on these fields. the ipvu bit controls the loading of the input pga volume data. when ipvu is set to 0, the pga volume data will be loaded into the respective control register, but will not actually change the gain setting. the lin12, rin12, lin34, rin34 volume settings are all updated when a 1 is written to ipvu. this makes it possible to update the gain of all input paths simultaneously. the input pga volume control register fields are described in table 7 and table 8. register address bit label default description 8 ipvu[0] n/a input pga volume update writing a 1 to this bit will cause all input pga volumes to be updated simultaneously (lin12, lin34, rin12 and rin34) 7 li12mute 1b lin12 pga mute 0 = disable mute 1 = enable mute 6 li12zc 0b lin12 pga zero cross detector 0 = change gain immediately 1 = change gain on zero cross only r24 (18h) 4:0 lin12vol [4:0] 01011b (0db) lin12 volume (see table 8 for volume range) 8 ipvu[1] n/a input pga volume update writing a 1 to this bit will cause all input pga volumes to be updated simultaneously (lin12, lin34, rin12 and rin34) 7 li34mute 1b lin34 pga mute 0 = disable mute 1 = enable mute 6 li34zc 0b lin34 pga zero cross detector 0 = change gain immediately 1 = change gain on zero cross only r25 (19h) 4:0 lin34vol [4:0] 01011b (0db) lin34 volume (see table 8 for volume range) 8 ipvu[2] n/a input pga volume update writing a 1 to this bit will cause all input pga volumes to be updated simultaneously (lin12, lin34, rin12 and rin34) 7 ri12mute 1b rin12 pga mute 0 = disable mute 1 = enable mute r26 (1ah) 6 ri12zc 0b rin12 pga zero cross detector 0 = change gain immediately 1 = change gain on zero cross only
WM8953 production data w pd, january 2009, rev 4.0 32 register address bit label default description 4:0 rin12vol [4:0] 01011b (0db) rin12 volume (see table 8 for volume range) 8 ipvu[3] n/a input pga volume update writing a 1 to this bit will cause all input pga volumes to be updated simultaneously (lin12, lin34, rin12 and rin34) 7 ri34mute 1b rin34 pga mute 0 = disable mute 1 = enable mute 6 ri34zc 0b rin34 pga zero cross detector 0 = change gain immediately 1 = change gain on zero cross only r27 (1bh) 4:0 rin34vol [4:0] 01011b (0db) rin34 volume (see table 8 for volume range) table 7 input pga volume control
production data WM8953 w pd, january 2009, rev 4.0 33 lin12vol[4:0], lin34vol[4:0], rin12vol[4:0], rin34vol[4:0] volume (db) 00000 -16.5 00001 -15.0 00010 -13.5 00011 -12.0 00100 -10.5 00101 -9.0 00110 -7.5 00111 -6.0 01000 -4.5 01001 -3.0 01010 -1.5 01011 0 01100 +1.5 01101 +3.0 01110 +4.5 01111 +6.0 10000 +7.5 10001 +9.0 10010 +10.5 10011 +12.0 10100 +13.5 10101 +15.0 10110 +16.5 10111 +18.0 11000 +19.5 11001 +21.0 11010 +22.5 11011 +24.0 11100 +25.5 11101 +27.0 11110 +28.5 11111 +30.0 table 8 input pga volume range
WM8953 production data w pd, january 2009, rev 4.0 34 input mixer enable the WM8953 has two analogue input mixers which allow the input pgas and line inputs to be combined in a number of ways and output to the adcs. the input mixers inmixl and inmixr are enabled by the ainl_ena and ainr_ena register bits, as described in table 9. register address bit label default description 9 ainl_ena (rw) 0b left input path enable 0 = input path disabled 1 = input path enabled r2 (02h) 8 ainr_ena (rw) 0b right input path enable 0 = input path disabled 1 = input path enabled table 9 input mixer enable input mixer volume control the input mixer volume controls are described in table 10 for the left channel and table 11 for the right channel. the input pga levels may be set to mute, 0db or 30db boost. the other gain controls provide adjustment from -12db to +6db in 3db steps. to prevent pop noise it is recommended that gain and mute controls for the input mixers are not modified while the signal paths are active. if volume control is required on the input signal path it is recommended that the input pga volume controls or the adc volume controls are used instead of the input mixer gain registers. register address bit label default description 8 l34mnb 0b lin34 pga output to inmixl mute 0 = mute 1 = un-mute 7 l34mnbst 0b lin34 pga output to inmixl gain 0 = 0db 1 = +30db 5 l12mnb 0b lin12 pga output to inmixl mute 0 = mute 1 = un-mute r41 (29h) 4 l12mnbst 0b lin12 pga output to inmixl gain 0 = 0db 1 = +30db r43 (2bh) 8:6 li2bvol [2:0] 000b (mute) lin2 pin to inmixl gain and mute 000 = mute 001 = -12db 010 = -9db 011 = -6db 100 = -3db 101 = 0db 110 = +3db 111 = +6db table 10 left input mixer volume control
production data WM8953 w pd, january 2009, rev 4.0 35 register address bit label default description 8 r34mnb 0b rin34 pga output to inmixr mute 0 = mute 1 = un-mute 7 r34mnbst 0b rin34 pga output to inmixr gain 0 = 0db 1 = +30db 5 r12mnb 0b rin12 pga output to inmixr mute 0 = mute 1 = un-mute r42 (2a) 4 r12mnbst 0b rin12 pga output to inmixr gain 0 = 0db 1 = +30db r44 (2ch) 8:6 ri2bvol [2:0] 000b (mute) rin2 pin to inmixr gain and mute 000 = mute 001 = -12db 010 = -9db 011 = -6db 100 = -3db 101 = 0db 110 = +3db 111 = +6db table 11 right input mixer volume control
WM8953 production data w pd, january 2009, rev 4.0 36 analogue to digital converter (adc) the WM8953 uses stereo 24-bit, 64x oversampled sigma-delta adcs. the use of multi-bit feedback and high oversampling rates reduces the effects of jitter and high frequency noise. the adc full scale input level is proportional to avdd. see ?electrical characteristics? for further details. any input signal greater than full scale may overload the adc and cause distortion. the adcs are enabled by the adcl_ena and adcr_ena register bits. if both adcs are to be enabled, they should be enabled simultaneously, i.e. with the same register write. if there is a requirement to enable the adcs independently of one another and use them simultaneously, the adcl_adcr_link bit should be set. the ext_acc ess_ena bit must be set before writing to the adcl_adcr_link bit. register address bit label default description 1 adcl_ena (rw) 0b left adc enable 0 = adc disabled 1 = adc enabled r2 (02h) 0 adcr_ena (rw) 0b right adc enable 0 = adc disabled 1 = adc enabled r117 (75h) 1 ext_acc ess_ena 0b ext ended register map access 0 = disabled 1 = enabled r122 (7ah) 15 adcl_adcr_link 0b 0 = adc sync disabled 1 = adc sync enabled table 12 adc enable control adc digital volume control the output of the adcs can be digitally amplified or attenuated over a range from -71.625db to +17.625db in 0.375db steps. the volume of each channel can be controlled separately. the gain for a given eight-bit code x is given by: 0.375 (x-192) db for 1 x 239; mute for x = 0 +17.625db for 239 x 255 the adc_vu bit controls the loading of digital volume control data. when adc_vu is set to 0, the adcl_vol or adcr_vol control data will be loaded into the respective control register, but will not actually change the digital gain setting. both left and right gain settings are updated when a 1 is written to adc_vu. this makes it possible to update the gain of both channels simultaneously. register address bit label default description 8 adc_vu n/a adc volume update writing a 1 to this bit will cause left and right adc volume to be updated simultaneously r15 (0fh) 7:0 adcl_vol [7:0] 1100_0000b (0db) left adc digital volume (see table 14 for volume range) 8 adc_vu n/a adc volume update writing a 1 to this bit will cause left and right adc volume to be updated simultaneously r16 (10h) 7:0 adcr_vol [7:0] 1100_0000b (0db) right adc digital volume (see table 14 for volume range) table 13 adc digital volume control
production data WM8953 w pd, january 2009, rev 4.0 37 adcl_vol or adcr_vol volume (db) adcl_vol or adcr_vol volume (db) a dcl_vol or adcr_vol volume (db) a dcl_vol or adcr_vol volume (db) 0h mute 40h -48.000 80h -24.000 c0h 0.000 1h -71.625 41h -47.625 81h -23.625 c1h 0.375 2h -71.250 42h -47.250 82h -23.250 c2h 0.750 3h -70.875 43h -46.875 83h -22.875 c3h 1.125 4h -70.500 44h -46.500 84h -22.500 c4h 1.500 5h -70.125 45h -46.125 85h -22.125 c5h 1.875 6h -69.750 46h -45.750 86h -21.750 c6h 2.250 7h -69.375 47h -45.375 87h -21.375 c7h 2.625 8h -69.000 48h -45.000 88h -21.000 c8h 3.000 9h -68.625 49h -44.625 89h -20.625 c9h 3.375 ah -68.250 4ah -44.250 8ah -20.250 cah 3.750 bh -67.875 4bh -43.875 8bh -19.875 cbh 4.125 ch -67.500 4ch -43.500 8ch -19.500 cch 4.500 dh -67.125 4dh -43.125 8dh -19.125 cdh 4.875 eh -66.750 4eh -42.750 8eh -18.750 ceh 5.250 fh -66.375 4fh -42.375 8fh -18.375 cfh 5.625 10h -66.000 50h -42.000 90h -18.000 d0h 6.000 11h -65.625 51h -41.625 91h -17.625 d1h 6.375 12h -65.250 52h -41.250 92h -17.250 d2h 6.750 13h -64.875 53h -40.875 93h -16.875 d3h 7.125 14h -64.500 54h -40.500 94h -16.500 d4h 7.500 15h -64.125 55h -40.125 95h -16.125 d5h 7.875 16h -63.750 56h -39.750 96h -15.750 d6h 8.250 17h -63.375 57h -39.375 97h -15.375 d7h 8.625 18h -63.000 58h -39.000 98h -15.000 d8h 9.000 19h -62.625 59h -38.625 99h -14.625 d9h 9.375 1ah -62.250 5ah -38.250 9ah -14.250 dah 9.750 1bh -61.875 5bh -37.875 9bh -13.875 dbh 10.125 1ch -61.500 5ch -37.500 9ch -13.500 dch 10.500 1dh -61.125 5dh -37.125 9dh -13.125 ddh 10.875 1eh -60.750 5eh -36.750 9eh -12.750 deh 11.250 1fh -60.375 5fh -36.375 9fh -12.375 dfh 11.625 20h -60.000 60h -36.000 a0h -12.000 e0h 12.000 21h -59.625 61h -35.625 a1h -11.625 e1h 12.375 22h -59.250 62h -35.250 a2h -11.250 e2h 12.750 23h -58.875 63h -34.875 a3h -10.875 e3h 13.125 24h -58.500 64h -34.500 a4h -10.500 e4h 13.500 25h -58.125 65h -34.125 a5h -10.125 e5h 13.875 26h -57.750 66h -33.750 a6h -9.750 e6h 14.250 27h -57.375 67h -33.375 a7h -9.375 e7h 14.625 28h -57.000 68h -33.000 a8h -9.000 e8h 15.000 29h -56.625 69h -32.625 a9h -8.625 e9h 15.375 2ah -56.250 6ah -32.250 aah -8.250 eah 15.750 2bh -55.875 6bh -31.875 abh -7.875 ebh 16.125 2ch -55.500 6ch -31.500 ach -7.500 ech 16.500 2dh -55.125 6dh -31.125 adh -7.125 edh 16.875 2eh -54.750 6eh -30.750 aeh -6.750 eeh 17.250 2fh -54.375 6fh -30.375 afh -6.375 efh 17.625 30h -54.000 70h -30.000 b0h -6.000 f0h 17.625 31h -53.625 71h -29.625 b1h -5.625 f1h 17.625 32h -53.250 72h -29.250 b2h -5.250 f2h 17.625 33h -52.875 73h -28.875 b3h -4.875 f3h 17.625 34h -52.500 74h -28.500 b4h -4.500 f4h 17.625 35h -52.125 75h -28.125 b5h -4.125 f5h 17.625 36h -51.750 76h -27.750 b6h -3.750 f6h 17.625 37h -51.375 77h -27.375 b7h -3.375 f7h 17.625 38h -51.000 78h -27.000 b8h -3.000 f8h 17.625 39h -50.625 79h -26.625 b9h -2.625 f9h 17.625 3ah -50.250 7ah -26.250 bah -2.250 fah 17.625 3bh -49.875 7bh -25.875 bbh -1.875 fbh 17.625 3ch -49.500 7ch -25.500 bch -1.500 fch 17.625 3dh -49.125 7dh -25.125 bdh -1.125 fdh 17.625 3eh -48.750 7eh -24.750 beh -0.750 feh 17.625 3fh -48.375 7fh -24.375 bfh -0.375 ffh 17.625 table 14 adc digital volume range
WM8953 production data w pd, january 2009, rev 4.0 38 high pass filter a digital high pass filter is applied by default to the adc path to remove dc offsets. this filter can also be programmed to remove low frequency noise in voice applications (e.g. wind noise or mechanical vibration). this filter is controlled using the adc_hpf_ena and adc_hpf_cut register bits. in hi-fi mode the high pass filter is optimised for removing dc offsets without degrading the bass response and has a cut-off frequency of 3.7hz at fs=44.1khz. in voice mode the high pass filter is optimised for voice communication and it is recommended to program the cut-off frequency below 300hz (e.g. adc_hpf_cut=11 at fs=8khz or adc_hpf_cut=10 at fs=16khz). register address bit label default description 8 adc_hpf_ena 1b adc digital high pass filter enable 0 = disabled 1 = enabled r14 (0eh) 6:5 adc_hpf_cut [1:0] 00b adc digital high pass filter cut-off frequency (fc) 00 = hi-fi mode (fc=4hz at fs=48khz) 01 = voice mode 1 (fc=127hz at fs=16khz) 10 = voice mode 2 (fc=130hz at fs=8khz) 11 = voice mode 3 (fc=267hz at fs=8khz) (note: fc scales with sample rate. see table 16 for cut-off frequencies at all supported sample rates) table 15 adc high pass filter control registers cut-off frequency (hz) sample frequency (khz) adc_hpf_cut =00 adc_hpf_cut =01 adc_hpf_cut =10 adc_hpf_cut =11 8.000 0.7 64 130 267 11.025 0.9 88 178 367 16.000 1.3 127 258 532 22.050 1.9 175 354 733 24.000 2.0 190 386 798 32.000 2.7 253 514 1063 44.100 3.7 348 707 1464 48.000 4.0 379 770 1594 table 16 adc high pass filter cut-off frequencies the high pass filter characteristics are shown in the "digital filter characteristics" section.
production data WM8953 w pd, january 2009, rev 4.0 39 digital audio paths the adc data can be routed in different ways to the digital audio interface. data from either of the two adcs can be routed to either the left or the right channel of the digital audio interface. independent functions enable either of the audio channels to be digitally inverted if required. see "digital audio interface" for more information on the audio interface. figure 20 shows the digital audio paths available in the WM8953 digital core. adcr_ena high pass filter (voice or hi-fi) high pass filter (voice or hi-fi) adc adc adcl_datinv adcl_vol [7:0] adcr_vol [7:0] digital audio interface a-law and u-law support tdm support en en adcr_datinv aifadcr_src aifadcl_src en en adcl_ena digital core adc_hpf_ena adc_hpf_cut [1:0] figure 20 digital audio paths
WM8953 production data w pd, january 2009, rev 4.0 40 the polarity of each adc output signal can be changed under software control using the adcl_datinv and adcr_datinv register bits. the aifadcl_src and aifadcr_src register bits may be used to select which adc is used for the left and right digital audio interface data. these register bits are described in table 17. register address bit label default description 15 aifadcl_src 0b left digital audio channel source 0 = left adc data is output on left channel 1 = right adc data is output on left channel r4 (04h) 14 aifadcr_src 1b right digital audio channel source 0 = left adc data is output on right channel 1 = right adc data is output on right channel 1 adcl_datinv 0b left adc invert 0 = left adc output not inverted 1 = left adc output inverted r14 (0eh) 0 adcr_datinv 0b right adc invert 0 = right adc output not inverted 1 = right adc output inverted table 17 adc routing and control thermal sensing the WM8953 incorporates a thermal sensor in order to provide protection from overheating. the sensor is enabled by setting tshut_ena. the status of the thermal sensor can be output on a gpio pin and/or read from the gpio registers. alternatively, the temperature sensor can be configured to cause an interrupt event. see ?general purpose input/output? for further details. note that, if thermal shutdown is required, this must be implemented by the host processor, in response to the thermal status indication generated by the WM8953. register address bit label default description r2 (02h) 14 tshut_ena (rw) 1b thermal sensor enable 0 = thermal sensor disabled 1 = thermal sensor enabled table 18 thermal shutdown
production data WM8953 w pd, january 2009, rev 4.0 41 general purpose input/output the WM8953 provides a number of versatile gpio functions to enable features such as button and accessory detection and clock output. the WM8953 has five multi-purpose pins for these functions. ? gpio3, gpio4 and gpio5: dedicated gpio pins. ? lin3/gpi7 and rin3/gpi8: analogue inputs or button/accessory detect inputs. the following functions are available on some or all of the gpio pins. ? button detect (latched with programmable de-bounce) ? micbias / accessory current or short circuit detect ? clock output ? temperature sensor output ? pll lock output ? logic '1' and logic '0' output ? interrupt event output ? serial data output (register readback) the functions available on each of the gpio pins are identified in table 19. gpio pins gpio pin function gpio3 gpio4 gpio5 gpi7 gpi8 button/accessory detect input y y y y y clock output y y y temperature ok y y y pll lock y y y logic 1 and logic 0 y y y interrupt y y y sdout (readback data) y y y pull-up and pull-down available y y y table 19 functions available on gpio pins the gpio pins are configured by a combination of register settings described in table 20 to table 23 in the following section. the order of precedence for the control of the gpio pins is as listed below. 1. pin pull-up or pull-down (gpion_pu, gpion_pd) 2. audio interface and gpio tristate (aif_tris) 3. gpio functionality (gpion_sel)
WM8953 production data w pd, january 2009, rev 4.0 42 gpio control registers register bit aif_tris, when set, tri-states all audio interface and gpio pins. register address bit label default description r9 (09h) 13 aif_tris 0b audio interface and gpio tristate 0 = audio interface and gpio pins operate normally 1 = tristate all audio interface and gpio pins table 20 gpio and gpi pin function select the gpio pins are also controlled by the register fields described in table 21. note the order of precedence described earlier applies. pull-up and pull-down resistors may be enabled on any of gpio3, gpio4 or gpio5. if enabled, these settings take precedence over all other gpio selections for that pin. note that, by default, the pull-down resistors on gpio3, gpio4 and gpio5 are enabled. when the gpio pins are used as inputs, de-bounce and interrupt masking may be controlled on all gpio pins (including gpi7 and gpi8) using gpion_deb_ena and gpion_irq_ena bits as shown in table 22. for each of gpio3, gpio4 and gpio5, the register field gpion_sel is used to select the pin functions of the individual gpio pins as shown in table 22. note that this control has the lowest precedence and is only effective when gpion_pu, gpion_pd and aif_tris are set to allow gpio functionality on that gpio pin. register address bit label default description 15 gpio4_deb_ena 0b 14 gpio4_irq_ena 0b 13 gpio4_pu 0b 12 gpio4_pd 1b 11:8 gpio4_sel[3:0] 0000b see table 22 for gpio4 control bit description 7 gpio3_deb_ena 0b 6 gpio3_irq_ena 0b 5 gpio3_pu 0b 4 gpio3_pd 1b r20 (14h) 3:0 gpio3_sel[3:0] 0000b see table 22 for gpio3 control bit description 7 gpio5_deb_ena 0b 6 gpio5_irq_ena 0b 5 gpio5_pu 0b 4 gpio5_pd 1b r21 (15h) 3:0 gpio5_sel[3:0] 0000b see table 22 for gpio5 control bit description 7 gpi8_deb_ena 0b 6 gpi8_irq_ena 0b 4 gpi8_ena 0b see table 22 for gpin control bit description 3 gpi7_deb_ena 0b 2 gpi7_irq_ena 0b r22 (16h) 0 gpi7_ena 0b see table 22 for gpin control bit description table 21 gpio and gpi control
production data WM8953 w pd, january 2009, rev 4.0 43 the following table describes the coding of the fields listed in table 21. register address label default description gpion_deb_ena (n = 3, 4, 5, 7, 8) 0b de-bounce 0 = disabled (not de-bounced) 1 = enabled (requires mclk input and toclk_ena = 1) gpion_irq_ena (n = 3, 4, 5, 7, 8) 0b irq enable 0 = disabled 1 = enabled gpion_pu (n = 3, 4, 5) 0b gpio pull-up resistor enable 0 = pull-up disabled 1 = pull-up enabled (approx 150k ? ) gpion_pd (n = 3, 4, 5) see table 21 gpio pull-down resistor enable 0 = pull-down disabled 1 = pull-down enabled (approx 150k ? ) gpion_sel[3:0] (n = 3, 4, 5) 0000b gpion pin function select 0000 = input pin 0001 = clock output (sysclk/opclkdiv) 0010 = logic '0' 0011 = logic '1' 0100 = pll lock output 0101 = temperature ok output 0110 = sdout data output 0111 = irq output 1000 = mic detect 1001 = mic short circuit detect 1010 to 1111 = reserved registers r20 (14h) to r21 (15h) (see table 21) gpin_ena (n = 7, 8) 0b gpin input pin enable 0 = pin disabled as gpin input 1 = pin enabled as gpin input table 22 gpio function control bits the polarity of gpio/gpi inputs may be configured using the gpio_pol register bits. this is described in table 23. register address bit label default description r23 (17h) 7:0 gpio_pol [7:0] (rw) 00h gpion input polarity 0 = non-inverted 1 = inverted gpio_pol[7] = gpi8 polarity gpio_pol[6] = gpi7 polarity gpio_pol[5] = reserved gpio_pol[4] = gpio5 polarity gpio_pol[3] = gpio4 polarity gpio_pol[2] = gpio3 polarity gpio_pol[1] = reserved gpio_pol[0] = reserved table 23 gpio polarity each of the available gpio functions is described in turn in the following sections.
WM8953 production data w pd, january 2009, rev 4.0 44 button control the WM8953 gpio supports button control detection with full status readback for up to four inputs (and one irq output). all inputs are latched at the irq register, with de-bounce available for normal operation. de-bouncing may be disabled in order to allow the device to respond to wake-up events while the processor is disabled and is unable to provide a clock for de-bouncing. to enable button control and accessory detection, the following register settings are required: ? lmn3 = 0 (only required if using gpi7) ? rmn3 = 0 (only required if using gpi8) ? aif_tris = 0 ? gpion_sel = 0000 for each required gpio button input programmable pull-up and pull-down resistors are available on gpio3, gpio4 and gpio5. these should be set according to the external circuit configuration. note that pull-up and pull-down resistors are not available on the gpi7 and gpi8 input pins. note that the analogue input paths to gpi7 and gpi8 must be disabled as described above when using these as digital inputs. in this application, one or more of the gpio pins may be configured as an interrupt event if desired. this is controlled by the gpion_irq_ena bits described in table 21. the gpio pin status fields contained in the irq register (r18) may be read at any time or else in response to an interrupt event. see table 30 for more details of the interrupt function. an example configuration of the button control gpio function is illustrated in figure 21. gpio5 gpio3 gpio4 figure 21 example of button control using gpio pins note: ? the gpios 3, 4, and 5 are referenced to dbvdd ? the gpis 7 and 8 are referenced to avdd
production data WM8953 w pd, january 2009, rev 4.0 45 micbias current and accessory detect a micbias current detect function is provided for accessory detection. when a microphone current is detected (e.g. when a headset is inserted), an interrupt event can be generated and the microphone status read back via the control interface. the micbias current detect threshold is programmable. a short-circuit current detection is also available, with a programmable threshold. these functions are enabled by register bit mcd; the thresholds are programmable via register fields mcdthr and mcdsctr as shown in table 24. current detect and short circuit detect thresholds are subject to a +/- 30% temperature, supply and part-to-part variation. this should be factored into any application design. the polarity of the current detect gpio signals may be controlled by register bits micdet_pol and micshrt_pol. note that these polarity inversion bits apply to the interrupt register behaviour only; they do not affect the direct gpio output of the current detect functions. the respective interrupt events may be masked or enabled by register bits micdet_irq_ena and micshrt_irq_ena. the micbias current threshold status bits contained in the irq register (r18) may be read at any time or else in response to an interrupt event. see table 30 for more details of the interrupt function. if direct output of the micbias current detect function is required to the external pins of the WM8953, the following register settings are required: ? aif_tris = 0 ? gpion_sel = 1000 for the selected gpio micbias current detect output pin ? gpion_sel = 1001 for the selected gpio micbias short circuit detect output pin ? gpion_pu = 0 for the selected gpio micbias output pin or pins ? gpion_pd = 0 for the selected gpio micbias output pin or pins the register fields used to configure the micbias current detect function are described in table 24. register address bit label default description 7:6 mcdscth [1:0] 00b micbias short circuit detect threshold 00 = 600ua 01 = 1200ua 10 = 1800ua 11 = 2400ua these values are for avdd=3.3v and scale proportionally with avdd. 5:3 mcdthr [2:0] 000b micbias current detect threshold 000 = 200ua 001 = 350ua 010 = 500ua 011 = 650ua 100 = 800ua 101 = 950ua 110 = 1100ua 111 = 1250ua these values are for avdd=3.3v and scale proportionally with avdd. r58 (3ah) 2 mcd 0b micbias current and short circuit detect enable 0 = disabled 1 = enabled 10 micshrt_pol (rw) 0b micbias short circuit detect polarity 0 = non-inverted 1 = inverted r23 (17h) 9 micdet_pol (rw) 0b micbias current detect polarity 0 = non-inverted 1 = inverted
WM8953 production data w pd, january 2009, rev 4.0 46 register address bit label default description 10 micshrt_irq_ena 0b micbias short circuit detect irq enable 0 = disabled 1 = enabled r22 (16h) 9 micdet_irq_ena 0b micbias current detect irq enable 0 = disabled 1 = enabled table 24 micbias current detect control the current detect function operates according to the following the truth table: label value description mic short circuit detect 0 mcdscth current threshold not exceeded mic short circuit detect 1 mcdscth current threshold exceeded mic current detect 0 mcdthr current threshold not exceeded mic current detect 1 mcdthr current threshold exceeded table 25 truth table for gpio output of micbias current detect function clock output a clock output (opclk) derived from sysclk may be output via gpio3, gpio4 or gpio5. sysclk is derived from mclk (either directly, or in conjunction with the pll), and is used to provide all internal clocking for the WM8953 (see "clocking and sample rates" section for more information). a programmable clock divider opclkdiv controls the frequency of the opclk output. this clock is enabled by register bit opclk_ena. see ?clocking and sample rates? for a definition of this register field. to enable clock output via one or more gpio pins, the following register settings are required: ? aif_tris = 0 ? gpion_sel = 0001 for the selected gpio clock output pin ? gpion_pu = 0 for the selected gpio clock output pin ? gpion_pd = 0 for the selected gpio clock output pin
production data WM8953 w pd, january 2009, rev 4.0 47 temperature sensor output to protect the device from overheating a thermal shutdown function is provided (see "thermal shutdown" section for more information). the polarity of the thermal shutdown sensor may be controlled by register bit tempok_pol. note that this polarity inversion bit applies to the interrupt register behaviour only; it does not affect the direct gpio output of the temperature sensor function. the associated interrupt event may be masked or enabled by register bit tempok_irq_ena. the temperature status bit contained in the irq register (r18) may be read at any time or else in response to an interrupt event. see table 30 for more details of the interrupt function. if direct output of the temperature status bit is required to the external pins of the WM8953, the following register settings are required: ? aif_tris = 0 ? gpion_sel = 0101 for the selected gpio temperature status output pin ? gpion_pu = 0 for the selected gpio temperature status output pin ? gpion_pd = 0 for the selected gpio temperature status output pin the register fields used to configure the temperature sensor gpio function are described in table 26. register address bit label default description r23 (17h) 11 tempok_pol (rw) 1b temperature sensor polarity 0 = non-inverted 1 = inverted r22 (16h) 11 tempok_irq_ ena 0b temperature sensor irq enable 0 = disabled 1 = enabled table 26 temperature sensor gpio control the temperature sensor function operates according to the following truth table: label value description temperature sensor output 0 overheat temperature exceeded temperature sensor output 1 overheat temperature not exceeded table 27 truth table for gpio output of temperature sensor function
WM8953 production data w pd, january 2009, rev 4.0 48 pll lock output an internal signal used to indicate the lock status of the pll can be output to a gpio pin or used to trigger an interrupt event. the polarity of the pll lock indication may be controlled by register bit pll_lck_pol. note that this polarity inversion bit applies to the interrupt register behaviour only; it does not affect the direct gpio output of the pll lock function. the associated interrupt event may be masked or enabled by register bit pll_lck_irq_ena. the pll lock status bit in the irq register (r18) may be read at any time or else in response to an interrupt event. see table 30 for more details of the interrupt function. if direct output of the pll lock status bit is required to the external pins of the WM8953, the following register settings are required: ? aif_tris = 0 ? gpion_sel = 0100 for the selected pll lock status output pin ? gpion_pu = 0 for the selected pll lock status output pin ? gpion_pd = 0 for the selected pll lock status output pin the register fields used to configure the pll lock gpio function are described in table 28. register address bit label default description r23 (17h) 8 pll_lck_pol (rw) 0b pll lock polarity 0 = non-inverted 1 = inverted r22 (16h) 8 pll_lck_irq_ ena 0b pll lock irq enable 0 = disabled 1 = enabled table 28 pll lock gpio control the pll lock function operates according to the following truth table: label value description pll lock output 0 pll not locked pll lock output 1 pll locked table 29 truth table for gpio output of pll lock function logic '1' and logic '0' output the gpio pins can be programmed to drive a logic high or logic low signal. the following register settings are required: ? aif_tris = 0 ? gpion_sel = 0010 for each logic ?0? output pin ? gpion_sel = 0011 for each logic ?1? output pin ? gpion_pu = 0 for each logic ?0? or logic ?1? gpio pin ? gpion_pd = 0 for each logic ?0? or logic ?1? gpio pin
production data WM8953 w pd, january 2009, rev 4.0 49 interrupt event output an interrupt can be generated by any of the following events described earlier: ? button control input (on gpio3, gpio4, gpio5, gpi7 or gpi8) ? micbias current / short circuit / accessory detect ? pll lock ? temperature sensor the interrupt status flag irq is asserted when any un-masked interrupt input is asserted. it is the or?d combination of all the un-masked interrupt inputs. if required, this flag may be inverted using the irq_inv register bit. the gpio pins can be configured to output the irq signal. the interrupt behaviour is driven by level detection (not edge detection) of the un-masked inputs. therefore, if an input remains asserted after the interrupt register has been reset, then the interrupt status flag irq will be triggered again even though no transition has occurred. if edge detection is required (eg. confirming that the input has been de-asserted), then the polarity inversion may be used after each event in order to detect each rising and falling edge separately. this is described further in the ?gpio summary? section. the status of the irq flag may be read back via the control interface. the status of each gpio pin and the internal signals pll_lck, tempok, micshrt and micdet may also be read back in the same way. the irq register (r18) is described in table 30. the status of the gpio pins or other interrupt inputs can be read back via the read/write bits r18[11:0]. the interrupt inputs are latched once set. each input may be reset by writing a 1 to the appropriate bit. the irq bit cannot be reset; it is the or?d combination of all other registers and will reset only if r18[11:0] are all 0. if direct output of the interrupt signal is required to external pins of the WM8953, the following register settings are required: ? aif_tris = 0 ? gpion_sel = 0111 for the selected interrupt (irq) output pin ? gpion_pu = 0 for the selected interrupt (irq) output pin ? gpion_pd = 0 for the selected interrupt (irq) output pin
WM8953 production data w pd, january 2009, rev 4.0 50 the irq register (r18) is described in table 30. register address bit label default description 12 irq (ro) read only irq readback (allows polling of irq status) 11 tempok (rr) read or reset temperature ok status read- 0 = device temperature not ok 1 = device temperature ok write - 1 = reset tempok latch 10 micshrt (rr) read or reset micbias short status read- 0 = micbias ok 1 = micbias shorted write- 1 = reset micshrt latch 9 micdet (rr) read or reset micbias detect status micbias microphone detect readback read- 0 = no microphone detected 1 = microphone detected write- 1 = reset micdet latch 8 pll_lck (rr) read or reset pll lock status read- 0 = pll not locked 1 = pll locked write- 1 = reset pll_lck latch r18 (12h) 7:0 gpio_status [7:0] (rr) read or reset gpio and gpi input pin status gpio_status[7] = gpi8 pin status gpio_status[6] = gpi7 pin status gpio_status[5] = reserved gpio_status[4] = gpio5 status gpio_status[3] = gpio4 status gpio_status[2] = gpio3 status gpio_status[1] = reserved gpio_status[0] = reserved r23 (17h) gpio control (2) 12 irq_inv (rw) 0b irq invert 0 = irq output active high 1 = irq output active low table 30 gpio interrupt and status readback
production data WM8953 w pd, january 2009, rev 4.0 51 serial data output (register readback) the gpio pins can be configured to output serial data during register readback in 3-wire (open-drain) or 4-wire mode. the readback mode is configured using the register bits rd_3w_ena and mode_3w4w as described in table 31. setting the rd_3w_ena bit to 1 enables 3-wire readback using the sdin pin in open-drain mode. setting the rd_3w_ena bit to 0 requires the use of a gpio pin as sdout. to enable sdout on a gpio pin, the following register settings are required: ? aif_tris = 0 ? gpion_sel = 0110 for the selected sdout output pin ? gpion_pu = 0 for the selected sdout output pin ? gpion_pd = 0 for the selected sdout output pin the register fields used to configure sdout on the gpio pins are described in table 31. refer to ?control interface? for more details of 3-wire and 4-wire interfacing. register address bit label default description 15 rd_3w_ena 1b 3- / 4-wire readback configuration 1 = 3-wire mode 0 = 4-wire mode, using gpio pin r22 (16h) 14 mode_3w4w 0b 3-wire mode 0 = push 0/1 1 = open-drain 4-wire mode 0 = push 0/1 1 = wired-or table 31 gpio 3-wire readback enable
WM8953 production data w pd, january 2009, rev 4.0 52 gpio summary the gpio functions are summarised in figure 22. mclk pll micbias lin3/gpi7 rin3/gpi8 micbias current detect + - + - mcdthr[2:0] 000 = 200ua 001 = 350ua 010 = 500ua 011 = 650ua 100 = 800ua 101 = 950ua 110 = 1100ua 111 = 1250ua short circuit threshold mic detect threshold mcdscth[1:0] 00 = 600ua 01 = 1200ua 10 = 1800ua 11 = 2400ua mcdscth [1:0] mcdthr [2:0] micbias_ena short circuit detect mic current detect temperature sensor t s h u t _ e n a /n o p c l k d i v [ 2 : 0 ] l o c k '0' '1' de- bounce s y s c l k _ s r c t o c l k g p i o n _ d e b _ e n a i r q _ i n v sdout gpio[2] gpio[3] gpio[4] gpi[6] gpi[7] irq gpio pin outputs * _ p o l m i c _ c d _ e n a o p c l k _ e n a e n p l l _ e n a ..._irq_ena pll_lck tempok micshrt micdet g p i o 5 _ s e l [ 3 : 0 ] g p i o 4 _ s e l [ 3 : 0 ] g p i o 3 _ s e l [ 3 : 0 ] g p i o n _ s e l [ 3 : 0 ] latches & gpio3 gpio4 gpio5 sysclk figure 22 gpio control diagram
production data WM8953 w pd, january 2009, rev 4.0 53 details of the gpio implementation are shown below. in order to avoid gpio loops if a gpio is configured as an output the corresponding input is disabled, as shown in figure 23 below. figure 23 gpio pad the gpio register, i.e. latch structure, is shown in figure 24 below. the de-bounce control fields gpion_deb_ena determine whether the signal is de-bounced or not. (note that toclk (via sysclk) needs to be present in order for the debounce circuit to work.) the polarity bits gpio_pol[7:0] control whether an interrupt is triggered by a logic 1 level (for gpio_pol[n] = 0) or a logic 0 level (for gpio_pol[n] = 1). the latch will cause the interrupt to be stored until it is reset by writing to the interrupt register. the latched signal is processed by the irq circuit, shown in figure 22 above. the interrupt status bits can be read at any time from register r18 (see table 30) and are reset by writing a ?1? to the applicable bit in register r18. note that the interrupt behaviour is driven by level detection (not edge detection). therefore, if an input remains asserted after the interrupt register has been reset, then the interrupt event will be triggered again even though no transition has occurred. if edge detection is required, this may be implemented as described in the following paragraphs. figure 24 gpio function three typical scenarios are presented in the following figure 25, figure 26 and figure 27. the examples are: ? latch a gpio input (figure 25) ? debounce and latch a gpio input (figure 26) ? use the gpion_pol bit to implement an irq edge detect function (figure 27)
WM8953 production data w pd, january 2009, rev 4.0 54 the gpio input or internal interrupt event (eg. micbias current detect) is latched as illustrated below: figure 25 gpio latch the de-bounce function on the gpio input pins enables transient behaviour to be filtered as illustrated below: figure 26 gpio de-bounce to implement an edge detect function on a gpio input, the gpion_pol bits may be used to alternate the gpio polarity after each edge transition. for example, after a logic 1 has caused an interrupt event, the polarity may be inverted prior to resetting the interrupt register bit. in this way, the next interrupt event generated by this gpio will occur when it returns to the logic 0 state. the gpion_pol bit must be reversed after every gpio edge transition, as illustrated below: figure 27 gpio edge detect
production data WM8953 w pd, january 2009, rev 4.0 55 gpio irq handling in the following diagram figure 28 a typical irq scenario is illustrated. figure 28 gpio irq handling
WM8953 production data w pd, january 2009, rev 4.0 56 digital audio interface the digital audio interface is used for outputting adc data from the WM8953. it uses three pins: ? adcdat: adc data output ? adclrc: adc data alignment clock ? bclk: bit clock, for synchronisation the clock signals bclk and adclrc can be outputs when the WM8953 operates as a master, or inputs when it is a slave (see master and slave mode operation, below). four different audio data formats are supported: ? left justified ? right justified ? i 2 s ? dsp mode all four of these modes are msb first. they are described in audio data formats, below. refer to the ?electrical characteristics? section for timing information. time division multiplexing (tdm) is available in all four data format modes. the WM8953 can be programmed to send and receive data in one of two time slots. pcm operation is supported using the dsp mode. master and slave mode operation the WM8953 digital audio interface can operate as a master or slave as shown in figure 29 and figure 30. figure 29 master mode figure 30 slave mode the dual audio interface approach of the WM8953 has been implemented in such a way that it gives the user and application as much flexibility as possible. the application needs to be carefully analysed and the WM8953 configured accordingly. the audio interface output control is illustrated in figure 31.
production data WM8953 w pd, january 2009, rev 4.0 57 figure 31 audio interface output control the audio interface output control is illustrated above. the master mode control register aif_mstr and the left-right clock control register adclrc_dir determine whether the WM8953 generates the associated clocks. these registers are described in table 32 below. register address bit label default description 15 aif_mstr 0b audio interface master mode select 0 = slave mode 1 = master mode r8 (08h) 11 adclrc_dir 0b adclrc direction (forces adclrc clock to be output in slave mode) 0 = adclrc normal operation 1 = adclrc clock output enabled table 32 audio interface output function control operation with tdm time division multiplexing (tdm) allows multiple devices to transfer data simultaneously on the same bus. the WM8953 supports tdm in master and slave modes for all data formats and word lengths. tdm is enabled using register bit aifadc_tdm. the tdm data slot is programmed using register bit aifadc_tdm_chan.
WM8953 production data w pd, january 2009, rev 4.0 58 figure 32 tdm with WM8953 as master figure 33 tdm with other adc as master figure 34 tdm with processor as master note: the WM8953 is a 24-bit device. if the user operates the WM8953 in 32-bit mode then the 8 lsbs are not driven. it is therefore recommended to add a pull-down resistor if necessary to the adcdat line in tdm mode. bclk divide the bclk frequency is controlled by bclk_div. the bclk frequency must be set appropriately to support the sample rate of the adc. internal clock divide and phase control mechanisms ensure that the bclk and adclrc edges will occur in a predictable and repeatable position relative to each other and to the data for a given combination of adc sample rate and bclk_div settings. see ?clocking and sample rates? section for more information.
production data WM8953 w pd, january 2009, rev 4.0 59 audio data formats (normal mode) in right justified mode, the lsb is available on the last rising edge of bclk before a adclrc transition. all other bits are transmitted before (msb first). depending on word length, bclk frequency and sample rate, there may be unused bclk cycles after each adclrc transition. figure 35 right justified audio interface (assuming n-bit word length) in left justified mode, the msb is available on the first rising edge of bclk following a adclrc transition. the other bits up to the lsb are then transmitted in order. depending on word length, bclk frequency and sample rate, there may be unused bclk cycles before each adclrc transition. figure 36 left justified audio interface (assuming n-bit word length) in i 2 s mode, the msb is available on the second rising edge of bclk following a adclrc transition. the other bits up to the lsb are then transmitted in order. depending on word length, bclk frequency and sample rate, there may be unused bclk cycles between the lsb of one sample and the msb of the next. figure 37 i2s justified audio interface (assuming n-bit word length)
WM8953 production data w pd, january 2009, rev 4.0 60 in dsp mode, the left channel msb is available on either the 1 st (mode b) or 2 nd (mode a) rising edge of bclk (selectable by aif_lrclk_inv) following a rising edge of adclrc. right channel data immediately follows left channel data. depending on word length, bclk frequency and sample rate, there may be unused bclk cycles between the lsb of the right channel data and the next sample. in device master mode, the adclrc output will resemble the frame pulse shown in figure 38 and figure 39. in device slave mode, figure 40 and figure 41, it is possible to use any length of frame pulse less than 1/fs, providing the falling edge of the frame pulse occurs greater than one bclk period before the rising edge of the next frame pulse. figure 38 dsp mode audio interface (mode a, aif_lrclk_inv=0, master) figure 39 dsp mode audio interface (mode b, aif_lrclk_inv=1, master) figure 40 dsp mode audio interface (mode a, aif_lrclk_inv=0, slave)
production data WM8953 w pd, january 2009, rev 4.0 61 figure 41 dsp mode audio interface (mode b, aif_lrclk_inv=1, slave) pcm operation is supported in dsp interface mode. WM8953 adc data that is output on the left channel will be read as mono pcm data by the receiving equipment. audio data formats (tdm mode) tdm is supported in master and slave mode and is enabled by register bit aif_adc_tdm. all audio interface data formats support time division multiplexing (tdm). two time slots are available (slot 0 and slot 1), selected by register bit aifadc_tdm_chan. when tdm is enabled, the adcdat pin will be tri-stated immediately before and immediately after data transmission, to allow another adc device to drive this signal line for the remainder of the sample period. note that it is important that two adc devices do not attempt to drive the data pin simultaneously. a short circuit may occur if the transmission time of the two adc devices overlap with each other. see ?audio interface timing - tdm mode? for details of the adcdat output relative to bclk signal. note that it is possible to ensure a gap exists between transmissions by setting the transmitted word length to a value higher than the actual length of the data. for example, if 32-bit word length is selected where only 24-bit data is available, then the WM8953 interface will tri-state after transmission of the 24-bit data, ensuring a gap after the WM8953?s tdm slot. when tdm is enabled, bclk frequency must be high enough to allow data from both time slots to be transferred. the relative timing of slot 0 and slot 1 depends upon the selected data format as shown in figure 42 to figure 46. figure 42 tdm in right-justified mode
WM8953 production data w pd, january 2009, rev 4.0 62 figure 43 tdm in left-justified mode left channel right channel 1/fs adclrc bclk adcdat 1 bclk 1 bclk slot 0 slot 1 slot 0 slot 1 figure 44 tdm in i 2 s mode figure 45 tdm in dsp mode a 1/fs adclrc bclk adcdat 1 bclk slot 0 left slot 0 right slot 1 left slot 1 right figure 46 tdm in dsp mode b
production data WM8953 w pd, january 2009, rev 4.0 63 digital audio interface control the register bits controlling audio data format, word length, left/right channel data source and tdm are summarised in table 33. register address bit label default description 15 aifadcl_src 0b left adc data source select 0 = left adc data is output on left channel 1 = right adc data is output on left channel 14 aifadcr_src 1b right adc data source select 0 = left adc data is output on right channel 1 = right adc data is output on right channel 13 aifadc_tdm 0b adc tdm enable 0 = normal adcdat operation 1 = tdm enabled on adcdat 12 aifadc_tdm_ chan 0b adcdat tdm channel select 0 = adcdat outputs data on slot 0 1 = adcdat output data on slot 1 8 aif_bclk_inv 0b bclk invert 0 = bclk not inverted 1 = bclk inverted right, left and i 2 s modes ? lrclk polarity 0 = normal lrclk polarity 1 = invert lrclk polarity 7 aif_lrclk_in v 0b dsp mode ? mode a/b select 0 = msb is available on 2nd bclk rising edge after lrc rising edge (mode a) 1 = msb is available on 1st bclk rising edge after lrc rising edge (mode b) 6:5 aif_wl [1:0] 10b digital audio interface word length 00 = 16 bits 01 = 20 bits 10 = 24 bits 11 = 32 bits note - see ?companding? for the selection of 8-bit mode. r4 (04h) 4:3 aif_fmt [1:0] 10b digital audio interface format 00 = right justified 01 = left justified 10 = i 2 s format 11 = dsp mode table 33 audio data format control audio interface output and gpio tristate register bit aif_tris can be used to tristate the audio interface and gpio pins as described in table 34. all gpio pins and digital audio interface pins will be tristated by this function, regardless of the state of other registers which control these pin configurations. register address bit label default description r9 (09h) 13 aif_tris 0 audio interface and gpio tristate 0 = audio interface and gpio pins operate normally 1 = tristate all audio interface and gpio pins table 34 tri-stating the audio interface and gpio pins
WM8953 production data w pd, january 2009, rev 4.0 64 master mode bclk and adclrc enable the audio interface pins bclk, adclrc and adcdat can be independently programmed to operate in master mode or slave mode using register bit aif_mstr. when the audio interface is operating in slave mode, the bclk and adclrc clock outputs to these pins are by default disabled to allow the digital audio source to drive these pins. it is also possible to force the adclrc to be output using register bit adclrc_dir, allowing mixed master and slave mode. the clock generators for the audio interface are enabled according to the control signals shown in figure 47. figure 47 clock output control register address bit label default description 15 aif_mstr 0b audio interface master mode select 0 = slave mode 1 = master mode 11 adclrc_dir 0b adclrc direction (forces adclrc clock to be output in slave mode) 0 = adclrc normal operation 1 = adclrc clock output enabled r8 (08h) 10:0 adclrc_rate [10:0] 040h adclrc rate adclrc clock output = bclk / adclrc_rate integer (lsb = 1) valid from 8..2047 table 35 digital audio interface clock output control
production data WM8953 w pd, january 2009, rev 4.0 65 companding the WM8953 supports a-law and -law companding. this is selected as shown in table 36. register address bit label default description 2 adc_comp 0b adc companding enable 0 = disabled 1 = enabled r5 (05h) 1 adc_compmode 0b adc companding type 0 = -law 1 = a-law table 36 companding control companding involves using a piecewise linear approximation of the following equations (as set out by itu-t g.711 standard) for data compression: -law (where =255 for the u.s. and japan): f(x) = ln( 1 + |x|) / ln( 1 + ) -1 x 1 a-law (where a=87.6 for europe): f(x) = a|x| / ( 1 + lna) } for x 1/a f(x) = ( 1 + lna|x|) / (1 + lna) } for 1/a x 1 the companded data is also inverted as recommended by the g.711 standard (all 8 bits are inverted for -law, all even data bits are inverted for a-law). the data will be transmitted as the first 8 msbs of data. companding converts 13 bits ( -law) or 12 bits (a-law) to 8 bits using non-linear quantization. this provides greater precision for low amplitude signals than for high amplitude signals, resulting in a greater usable dynamic range than 8 bit linear quantization. the companded signal is an 8-bit word comprising sign (1 bit), exponent (3 bits) and mantissa (4 bits). 8-bit mode is selected whenever adc_comp=1. the use of 8-bit data allows samples to be passed using as few as 8 bclk cycles per lrc frame. when using dsp mode b, 8-bit data words may be transferred consecutively every 8 bclk cycles. 8-bit mode (without companding) may be enabled by setting adc_compmode=1, when adc_comp=0. bit7 bit[6:4] bit[3:0] sign exponent mantissa table 37 8-bit companded word composition
WM8953 production data w pd, january 2009, rev 4.0 66 u-law companding 0 20 40 60 80 100 120 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 normalised input companded output 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 normalised output figure 48 -law companding a-law companding 0 20 40 60 80 100 120 0 0.2 0.4 0.6 0.8 1 normalised input companded output 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 normalised output figure 49 a-law companding
production data WM8953 w pd, january 2009, rev 4.0 67 clocking and sample rates the internal clocks for the adcs, dsp core functions and digital audio interface are derived from a common internal clock source, sysclk. sysclk can either be derived directly from mclk, or may be generated from a pll using mclk as an external reference. many commonly-used audio sample rates can be derived directly from typical mclk frequencies; the pll provides additional flexibility for a wide range of mclk frequencies. all clock configurations must be set up before enabling playback to avoid glitches. the adc sample rate is selectable, relative to sysclk, using adc_clkdiv. this must be set according to the required sampling frequency and depending on the selected clocking mode (aif_lrclkrate). in master mode, bclk is also derived from sysclk via a programmable division set by bclk_div. the bclk frequency must be set appropriately to support the sample rate of the adc. the adclrc signal does not automatically match the adc sample rate; this must be configured using adclrc_rate as described under ?digital audio interface control?. a clock (opclk) derived from sysclk can be output on the gpio pins to provide clocking for other parts of the system. this clock is enabled by opclk_ena and its frequency is set by opclkdiv. a slow clock (toclk) derived from sysclk can be used to de-bounce the button/accessory detect inputs, and to set the timeout period for volume updates when zero-cross detect is used. this clock is enabled by toclk_ena and its frequency is set by toclk_rate. table 38 to table 43 show the clocking and sample rate controls for mclk input, bclk output (in master mode), adcs, and gpio clock output. the overall clocking scheme for the WM8953 is illustrated in figure 50. mclk pll r=f 2 /f 1 sysclk f 2 f 1 master mode clock outputs f pllout f/n f/4 f/2 gpio clock output f/n timeout and de-bounce clock button/accessory detect de-bounce, volume update timeout toclk_ena f/2 21 f/2 19 mclk mclk is the master clock source sysclk all internal clocks are derived from sysclk. sysclk can be derived directly from mclk or from the pll output. it has a programmable divide by 2 option (mclkdiv). adc_clkdiv adc sample rate is set by adc_clkdiv (master or slave mode). adclrc_rate adclrc in master mode is derived from bclk and is controlled by adclrc_rate. bclk_div bclk rate is set by bclk_div in master mode. the bclk rate should be high enough to support the selected adc sample rate. opclkdiv gpio clock output frequency is set by opclkdiv. toclk_rate a slow clock is used for button/accessory detect de-bounce and for volume update timeouts (when zero-cross detect is enabled). the frequency of this slow clock is set by toclk_rate. toclk_rate bclk_div[3:0] 0000 = sysclk 0001 = sysclk / 1.5 0010 = sysclk / 2 0011 = sysclk / 3 0100 = sysclk / 4 0101 = sysclk / 5.5 0110 = sysclk / 6 0111 = sysclk / 8 1000 = sysclk / 11 1001 = sysclk / 12 1010 = sysclk / 16 1011 = sysclk / 22 1100 = sysclk / 24 1101 = sysclk / 32 1110 = sysclk / 44 1111 = sysclk / 48 bclkdiv [3:0] opclkdiv[3:0] 0000 = sysclk 0001 = sysclk / 2 0010 = sysclk / 3 0011 = sysclk / 4 0100 = sysclk / 5.5 0101 = sysclk / 6 0110 = sysclk / 8 0111 = sysclk / 12 1000 = sysclk /16 1001 ? 1111 = reserved opclkdiv mclkdiv[1:0] 00 = mclk 01 = reserved 10 = mclk / 2 11 = reserved mclkdiv[1:0] sysclk_src prescale adc_clkdiv[2:0] 000 = sysclk 001 = sysclk / 1.5 010 = sysclk / 2 011 = sysclk / 3 100 = sysclk / 4 101 = sysclk / 5.5 110 = sysclk / 6 111 = reserved opclk_ena en bclk adclrc f/n adclrc_rate [10:0] mclk_inv 256fs adc_clkdiv [2:0] f/4 adc dsp 64fs f/n adc f/n figure 50 clocking scheme
WM8953 production data w pd, january 2009, rev 4.0 68 sysclk control mclk may be inverted by setting register bit mclk_inv. note that it is not recommended to change the control bit mclk_inv while the WM8953 is processing data as this may lead to clock glitches and signal pop and clicks. the sysclk_src bit is used to select the source for sysclk. the source may be either mclk or the pll output. the selected source is divided by the sysclk pre-divider mclk_div to generate sysclk. the selected source may also be adjusted by the mclk_div divider. these register fields are described in table 38. see ?pll? for more details of the phase locked loop clock generator. the WM8953 supports glitch-free sysclk source selection. w hen both clock sources are running and sysclk_src is modified to select one of these clocks, a glitch-free clock transition will take place. the de-glitching circuit will ensure that the minimum pulse width will be no less than the pulse width of the faster of the two clock sources. when the initial clock source is to be disabled before changing to the new clock source, the clk_force bit must also be used to force the clock source transition to take place. in this case, glitch-free operation cannot be guaranteed. register address bit label default description 14 sysclk_src 0b sysclk source select 0 = mclk 1 = pll output 13 clk_force 0b forces clock source selection 0 = existing sysclk source (mclk or pll output) must be active when changing to a new clock source. 1 = allows existing mclk source to be disabled before changing to a new clock source. 12:11 mclk_div [1:0] 00b sysclk pre-divider. clock source (mclk or pll output) will be divided by this value to generate sysclk. 00 = divide sysclk by 1 01 = reserved 10 = divide sysclk by 2 11 = reserved r7 (07h) 10 mclk_inv 0b mclk invert 0 = master clock not inverted 1 = master clock inverted table 38 mclk and sysclk control
production data WM8953 w pd, january 2009, rev 4.0 69 adc sample rate the adc sample rate is selectable, relative to sysclk, by setting the register fields adc_clkdiv. this must be set according to the sysclk fr equency, and according to the selected clocking mode. two clocking modes are provided - normal mode (aif_lrclkrate = 0) allows selection of the commonly used sample rates from typical audio system clocking frequencies (eg. 12.288mhz); usb mode (aif_lrclkrate = 1) allows many of these sample rates to be generated from a 12mhz usb clock. depending on the available clock sources, the usb mode may be used to save power by supporting 44.1khz operation without requiring the pll. the aif_lrclkrate field must be set as described in table 39 to ensure correct operation of internal functions according to the sysclk / fs ra tio. table 40 describes the available sample rates using four different common mclk frequencies. in normal mode, the programmable division set by adc_clkdiv must ensure that a 256 * adc fs clock is generated for the adc dsp. in usb mode, the programmable division set by adc_clkdiv must ensure that a 272 * adc fs clock is generated for the adc dsp. note that in usb mode, the adc sample rates do not match exactly with the commonly used sample rates (e.g. 44.118 khz instead of 44.100 khz). at most, the difference is less than 0.5%. data recorded at 44.100 khz sample rate and replayed at 44.118 khz will experience a slight (sub 0.5%) pitch shift as a result of this difference. note also that the usb mode cannot be used to generate a 48khz samples rate from a 12mhz mclk; the pll should be used in this case. register address bit label default description r7 (07h) 7:5 adc_clkdiv [2:0] 000b adc sample rate divider 000 = sysclk / 1.0 001 = sysclk / 1.5 010 = sysclk / 2.0 011 = sysclk / 3.0 100 = sysclk / 4.0 101 = sysclk / 5.5 110 = sysclk / 6.0 111= reserved r10 (0ah) 10 aif_lrclkrat e 0b lrclk rate 0 = normal mode (256 * fs) 1 = usb mode (272 * fs) table 39 adc sample rate control
WM8953 production data w pd, january 2009, rev 4.0 70 sysclk adc sample rate divider clocking mode adc sample rate 000 = sysclk / 1 48 khz 001 = sysclk / 1.5 32 khz 010 = sysclk / 2 24 khz 011 = sysclk / 3 16 khz 100 = sysclk / 4 12 khz 101 = sysclk / 5.5 not used 110 = sysclk / 6 8 khz 12.288 mhz 111 = reserved normal (256 * fs) reserved 000 = sysclk / 1 44.1 khz 001 = sysclk / 1.5 not used 010 = sysclk / 2 22.05 khz 011 = sysclk / 3 not used 100 = sysclk / 4 11. 025 khz 101 = sysclk / 5.5 8. 018 khz 110 = sysclk / 6 not used 11.2896 mhz 111 = reserved normal (256 * fs) reserved 000 = sysclk / 1 44. 118 khz 001 = sysclk / 1.5 not used 010 = sysclk / 2 22. 059 khz 011 = sysclk / 3 not used 100 = sysclk / 4 11. 029 khz 101 = sysclk / 5.5 8. 021 khz 110 = sysclk / 6 not used 12 mhz 111 = reserved usb mode (272 * fs) reserved 000 = sysclk / 1 8 khz 001 = sysclk / 1.5 not used 010 = sysclk / 2 not used 011 = sysclk / 3 not used 100 = sysclk / 4 not used 101 = sysclk / 5.5 not used 110 = sysclk / 6 not used 2.048 mhz 111 = reserved normal (256 * fs) reserved table 40 adc sample rates
production data WM8953 w pd, january 2009, rev 4.0 71 bclk control in master mode, bclk is derived from sysclk via a programmable division set by bclk_div, as described in table 41. bclk_div must be set to an appropriate value to ensure that there are sufficient bclk cycles to transfer the complete data words from the adcs. in slave mode, bclk is generated externally and appears as an input to the adc. the host device must provide sufficient bclk cycles to transfer complete data words from the adcs. register address bit label default description r6 (06h) 4:1 bclk_div [3:0] 0100b bclk frequency (master mode) 0000 = sysclk 0001 = sysclk / 1.5 0010 = sysclk / 2 0011 = sysclk / 3 0100 = sysclk / 4 0101 = sysclk / 5.5 0110 = sysclk / 6 0111 = sysclk / 8 1000 = sysclk / 11 1001 = sysclk / 12 1010 = sysclk / 16 1011 = sysclk / 22 1100 = sysclk / 24 1101 = sysclk / 32 1110 = sysclk / 44 1111 = syscl:k / 48 table 41 bclk control opclk control a clock output (opclk) derived from sysclk may be output via gpio3, gpio4 or gpio5. this clock is enabled by register bit opclk_ena, and its frequency is controlled by opclkdiv. this output of this clock is also dependent upon the gpio register settings described under ?general purpose input/output?. register address bit label default description r6 (06h) 12:9 opclkdiv [3:0] 0000b gpio output clock divider 0000 = sysclk 0001 = sysclk / 2 0010 = sysclk / 3 0011 = sysclk / 4 0100 = sysclk / 5.5 0101 = sysclk / 6 0110 = sysclk / 8 0111 = sysclk / 12 1000 = sysclk / 16 1001 to 1111 = reserved r2 (02h) 11 opclk_ena (rw) 0b gpio clock output enable 0 = disabled 1 = enabled table 42 opclk control
WM8953 production data w pd, january 2009, rev 4.0 72 toclk control a slow clock (toclk) is derived from sysclk to enable input de-bouncing and volume update timeout functions. this clock is enabled by register bit toclk_ena, and its frequency is controlled by toclk_rate, as described in table 43. register address bit label default description 15 toclk_rate 0b timeout clock rate (selects clock to be used for volume update timeout and gpio input de- bounce) 0 = sysclk / 2 21 (slower response) 1 = sysclk / 2 19 (faster response) r6 (06h) 14 toclk_ena 0b timeout clock enable (this clock is required for volume update timeout and gpio input de-bounce) 0 = disabled 1 = enabled table 43 toclk control usb mode it is possible to reduce power consumption by disabling the pll in some applications. one such application is when sysclk is generated from a 12mhz usb clock source. setting the aif_lrclkrate bit as described earlier (see ?adc sample rates?) allows a sample rate close to 44.1khz to be generated with no additional pll power consumption. in this configuration, sysclk must be driven directly from mclk and by disabling the pll. this is achieved by setting sysclk_src=0, p ll_ena=0. register address bit label default description r10 (0ah) 10 aif_lrclkrate 0b lrclk rate 0 = normal mode (256 * fs) 1 = usb mode (272 * fs) table 44 usb mode control
production data WM8953 w pd, january 2009, rev 4.0 73 pll the integrated pll can be used to generate sysclk for the WM8953 from a wide range of mclk reference frequencies. the pll is enabled by the pll_ena register bit. if required, the input reference clock can be divided by 2 by setting the register bit prescale. the pll frequency ratio r is equal to f 2 /f 1 (see figure 50). this ratio is the real number represented by register fields plln and pllk, where plln is an integer (lsb = 1) and pllk is the fractional portion of the number (msb = 0.5). the fractional portion is only valid when enabled by the field sdm. de-selection of fractional mode results in lower power consumption. for pll stability, input frequencies and divisions must be chosen so that 5 plln 13. best performance is achieved for 7 n 9. also, the pll performs best when f 2 is set between 90mhz and 100mhz. if pllk is regarded as a 16-bit integer (instead of a fractional quantity), then plln and pllk may be determined as follows: ? plln = int r ? pllk = int (2 16 (r - plln)) the pll control register settings are described in table 45. register address bit label default description r2 (02h) 15 pll_ena (rw) 0 pll enable 0 = disabled 1 = enabled 7 sdm 0 enable pll integer mode 0 = integer mode 1 = fractional mode 6 prescale 0b divide mclk by 2 at pll input 0 = divide by 1 1 = divide by 2 r60 (3ch) 3:0 plln[3:0] 8h integer (n) part of pll frequency ratio. r61 (3dh) 7:0 pllk [15:8] 31h fractional (k) part of pll frequency ratio. (most significant bits) r62 (3eh) 7:0 pllk [7:0] 26h fractional (k) part of pll frequency ratio. (least significant bits) table 45 pll control
WM8953 production data w pd, january 2009, rev 4.0 74 example pll calculation to generate 12.288mhz sysclk from a 12mhz reference clock: there is a fixed divide by 4 at the pll output (see figure 50) followed by a selectable divide by 2 in the same path. pll output f 2 should be set in the range 90mhz - 100mhz. enabling the divide by 2 (mclk_div = 10b) sets the required f 2 = 4 x 2 x 12.288mhz = 98.304mhz. there is a selectable pre-scale (divide mclk by 2) at the pll input (f 1 - see figure 75). the pll frequency ratio f 2 /f 1 must be set in the range 5 - 13. disabling the mclk pre-scale (prescale = 0b) sets the required ratio f 2 /f 1 = 8.192. the required settings for this example are: ? mclk_div = 10b ? prescale = 0b ? pll_ena = 1 ? sdm = 1 ? plln = 8 = 8h ? pllk = 0.192 = 3126h example pll settings table 46 provides example pll settings for generating common sysclk fr equencies from a variety of mclk reference frequencies. mclk (mhz) sysclk (mhz) mclkdiv f2 = sysclk * 4 * mclkdiv prescale f1 = mclk/ prescale r = f2/f1 n k 12 11.2896 2 90.3168 1 12 7.5264 7h 86c2h 12 12.288 2 98.304 1 12 8.192 8h 3126h 13 11.2896 2 90.3168 1 13 6.947446 6h f28bh 13 12.288 2 98.304 1 13 7.561846 7h 8fd5h 14.4 11.2896 2 90.3168 1 14.4 6.272 6h 45a1h 14.4 12.288 2 98.304 1 14.4 6.826667 6h d3a0h 19.2 11.2896 2 90.3168 2 9.6 9.408 9h 6872h 19.2 12.288 2 98.304 2 9.6 10.24 ah 3d70h 19.68 11.2896 2 90.3168 2 9.84 9.178537 9h 2db4h 19.68 12.288 2 98.304 2 9.84 9.990243 9h fd80h 19.8 11.2896 2 90.3168 2 9.9 9.122909 9h 1f76h 19.8 12.288 2 98.304 2 9.9 9.929697 9h ee00h 24 11.2896 2 90.3168 2 12 7.5264 7h 86c2h 24 12.288 2 98.304 2 12 8.192 8h 3126h 26 11.2896 2 90.3168 2 13 6.947446 6h f28bh 26 12.288 2 98.304 2 13 7.561846 7h 8fd5h 27 11.2896 2 90.3168 2 13.5 6.690133 6h b0ach 27 12.288 2 98.304 2 13.5 7.281778 7h 4822h table 46 pll frequency examples
production data WM8953 w pd, january 2009, rev 4.0 75 control interface the WM8953 is controlled by writing to its control registers. readback is available for certain registers, including device id, power management registers and some gpio status bits. the control interface can operate as either a 2-, 3- or 4-wire control interface, with additional variants as detailed below: 1. 2-wire - open-drain 2. 3-wire - push 0/1 - open drain 3. 4-wire - push 0/1 - wired-or readback is provided on the bi-directional pin sdin in 2-/3-wire modes and on a gpio pin in 4-wire mode. selection of control mode the mode pin determines the 2- or 3-/4-wire mode as shown in table 47. mode interface format low 2 wire high 3- or 4- wire table 47 control interface mode selection 2-wire serial control mode the WM8953 is controlled by writing to registers through a 2-wire serial control interface. a control word consists of 24 bits. the first 8 bits (b23 to b16) are address bits that select which control register is accessed. the remaining 16 bits (b15 to b0) are data bits, corresponding to the 16 bits in each control register. many devices can be controlled by the same bus, and each device has a unique 7-bit address (this is not the same as the 8-bit address of each register in the WM8953). the default device address is 0011010 (0x34h). the WM8953 operates as a slave device only. the controller indicates the start of data transfer with a high to low transition on sdin while sclk remains high. this indicates that a device address and data will follow. all devices on the 2-wire bus respond to the start condition and shift in the next eight bits on sdin (7-bit address + read/write bit, msb first). if the device address received matches the address of the WM8953, then the WM8953 responds by pulling sdin low on the next clock pulse (ack). if the address is not recognised or the r/w bit is ?1? when operating in write only mode, the WM8953 returns to the idle condition and wait for a new start condition and valid address. the WM8953 supports a multitude of read and write operations, which are: ? single write ? single read ? multiple write using auto-increment ? multiple read using auto-increment
WM8953 production data w pd, january 2009, rev 4.0 76 these modes are shown in the section below. terminology used in the following figures: terminology description s start condition sr repeated start a acknowledge p stop condition rw readnotwrite 0 = write 1 = read table 48 terminology figure 51 2-wire serial control interface (single write) rw device id sr a p msbyte data (1) lsbyte data a device id s a index (0) a rw a figure 52 2-wire serial control interface (single read) figure 53 2-wire serial control interface (multiple write using auto-increment) figure 54 2-wire serial control interface (multiple read using auto-increment) in 2-wire mode, the WM8953 has two possible device addresses, which can be selected using the csb/addr pin. csb/addr state device address low 0011010 (0 x 34h) high 0011011 (0 x 36h) table 49 2-wire control interface address selection
production data WM8953 w pd, january 2009, rev 4.0 77 3-wire / 4-wire serial control modes the WM8953 is controlled by writing to registers through a 3- or 4-wire serial control interface. a control word consists of 24 bits. the first bit is the read/write bit (r/w), which is followed by 7 address bits (a6 to a0) that determine which control register is accessed. the remaining 16 bits (b15 to b0) are data bits, corresponding to the 16 bits in each control register. the 3- or 4-wire modes are selected by the rd_3w_ena register bit. additionally the mode_3w4w control bit can be used to select between push 0/1 and open-drain or wired-or modes, as described in table 50 below. register address bit label default description 15 rd_3w_ena 1b 3- / 4-wire readback configuration 1 = 3-wire mode 0 = 4-wire mode, using gpio pin r22 (16h) 14 mode_3w4w 0b 3-wire mode 0 = push 0/1 1 = open-drain 4-wire mode 0 = push 0/1 1 = wired-or table 50 3-wire / 4-wire control interface selection 3-wire control mode is selected by setting rd_3w_ena = 1. in 3-wire mode, every rising edge of sclk clocks in one data bit from the sdin pin. a rising edge on csb/addr latches in a complete control word consisting of the last 24 bits. in write operations (r/w=0), all sdin bits are driven by the controlling device. in read operations (r/w=1), the sdin pin is driven by the controlling device to clock in the register address, after which the WM8953 drives the sdin pin to output the applicable data bits. the 3-wire control mode timing is illustrated in figure 55. figure 55 3-wire serial control interface 4-wire control mode is selected by setting rd_3w_ena = 0. in write operations (r/w=0), this mode is the same as 3-wire mode described above. in read operations (r/w=1), a gpio pin must be selected to output sdout by setting gpion_sel=0110b (n= 3, 4 or 5). in this mode, the sdin pin is ignored following receipt of the valid register address. sdout is driven by the WM8953. in 4-wire push 0/1 mode, sdout is driven low when not outputting register data bits. in wired-or mode, sdout is undriven when not outputting register data bits. the 4-wire control mode timing is illustrated in figure 56 and figure 57.
WM8953 production data w pd, january 2009, rev 4.0 78 r/w a6 a5 a4 a3 a2 a1 a0 sdin sclk csb control register address control register data bits ( read / write ) sdout b15 b14 b13 b12 b11 b10 b9 b8 b0 b7 b6 b5 b4 b3 b2 b1 b15 b14 b13 b12 b11 b10 b9 b8 b0 b7 b6 b5 b4 b3 b2 b1 figure 56 4-wire readback (push 0/1) a6 a5 a4 a3 a2 a1 a0 sdin sclk csb control register address control register data bits ( read / write ) sdout undriven b15 b14 b13 b12 b11 b10 b9 b8 b0 b7 b6 b5 b4 b3 b2 b1 b15 b14 b13 b12 b11 b10 b9 b8 b0 b7 b6 b5 b4 b3 b2 b1 ud r/w figure 57 4-wire readback (wired-or)
production data WM8953 w pd, january 2009, rev 4.0 79 power management power management registers the WM8953 has two control registers that allow users to select which functions are active. for minimum power consumption, unused functions should be disabled. to minimise pop or click noise, it is important to enable or disable functions in the correct order. register address bit label default description 4 micbias_ena (rw) 0b micbias enable 0 = off (high impedance output) 1 = on 2:1 vmid_mode [1:0] (rw) 00b vmid divider enable and select 00 = vmid disabled (for off mode) 01 = 2 x 50k ? divider (normal mode) 10 = 2 x 250k ? divider (standby mode) 11 = 2 x 5k ? divider (for fast start-up) r1 (1h) 0 vref_ena (rw) 0b vref enable (bias for all analogue functions) 0 = vref bias disabled 1 = vref bias enabled 15 pll_ena (rw) 0b pll enable 0 = disabled 1 = enabled 14 tshut_ena (rw) 0b thermal sensor enable 0 = thermal sensor disabled 1 = thermal sensor enabled 11 opclk_ena (rw) 0b gpio clock output enable 0 = disabled 1 = enabled 9 ainl_ena (rw) 0b left input path enable 0 = disabled 1 = enabled 8 ainr_ena (rw) 0b left input path enable 0 = disabled 1 = enabled 7 lin34_ena (rw) 0b lin34 input pga enable 0 = disabled 1 = enabled 6 lin12_ena (rw) 0b lin12 input pga enable 0 = disabled 1 = enabled 5 rin34_ena (rw) 0b rin34 input pga enable 0 = disabled 1 = enabled 4 rin12_ena (rw) 0b rin12 input pga enable 0 = disabled 1 = enabled 1 adcl_ena (rw) 0b left adc enable 0 = disabled 1 = enabled r2 (02h) 0 adcr_ena (rw) 0b right adc enable 0 = disabled 1 = enabled table 51 power management
WM8953 production data w pd, january 2009, rev 4.0 80 chip reset and id the device id can be read back from register 0. writing to this register will reset the device. register address bit label default description r0 (00h) reset / id 15:0 sw_reset_c hip_id [15:0] (rr) 8990h writing to this register resets all registers to their default state. reading from this register will indicate device family id 8990h. table 52 chip reset and id
production data WM8953 w pd, january 2009, rev 4.0 81 power domains figure 58 WM8953 power domains
WM8953 production data w pd, january 2009, rev 4.0 82 register map dec addr hex addr name 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bin default 00reset 1000_1001_1001_0000 1 1 power management (1) 0 0 0 0 0000000 micbias_en a 0 vref_ena 0000_0000_0000_0000 2 2 power management (2) pll_ena tshut_ena 1 0 opclk_ena 0 ainl_ena ainr_ena lin34_ena lin12_ena rin34_ena rin12_ena 0 0 adcl_ena adcr_ena 0110_00 00_0000_0000 33reserved 0000000000000000 0000_0000_0000_0000 4 4 audio interface (1) aifadcl_sr c aifadcr_sr c aifadc_tdm aifadc_tdm_c han 000 aif_bclk_in v aif_lrclk_i nv 0 0 0 0100_0000_0101_0000 5 5 audio interface (2) 0 1 0 0 000000000adc_comp adc_compm ode 0 0100_0000_0000_0000 6 6 clocking (1) toclk_rate toclk_ena 0 1110 0 0000_0001_1100_1000 7 7 clocking (2) 0 sysclk_src clk_force mclk_inv 0 0 0 0 0 0 0 00p0_0000_0000_0000 8 8 audio interface (3) aif_mstr 0 0 0 adclrc_dir 0000_0000_0100_0000 99audio interface (4) 00aif_tris0000001000000 0000_0000_0100_0000 10 a lrclk rate 0 0 0 0 0 aif_lrclkr ate 0 0 0 0 0 0 0 1 0 0 0000_0000_0000_0100 11breserved 0000000p11000000 0000_000p_1100_0000 12creserved 0000000p11000000 0000_000p_1100_0000 13dreserved 0000000000000000 0000_0000_0000_0000 14eadc ctrl 0000000 adc_hpf_en a 0000 adcl_datin v adcr_datin v 0000_0001_0000_0000 15 f left adc digital volume 0 0 0 0 0 0 0 adc_vu 0000_000p_1100_0000 16 10 right adc digital volume 0 0 0 0 0 0 0 adc_vu 0000_000p_1100_0000 1711reserved 0000000000000000 0000_0000_0000_0000 18 12 gpio ctrl 1 0 0 0 irq tempok micshrt micdet pll_lck 0000_pppp_pppp_pppp 1913reserved 0001000000000000 0001_0000_0000_0000 20 14 gpio3 & gpio4 gpio4_deb_ ena gpio4_irq_e na gpio4_pu gpio4_pd gpio3_deb_ ena gpio3_irq_e na gpio3_pu gpio3_pd 0001_0000_0001_0000 2115gpio5 00010000 gpio5_deb_ ena gpio5_irq_e na gpio5_pu gpio5_pd 0001_0000_0001_0000 22 16 gpioctrl 2 rd_3w_ena mode_3w4w 0 0 tempok_irq _ena micshrt_ir q_ena micdet_irq _ena pll_lck_irq _ena gpi8_deb_e na gpi8_irq_en a 0 gpi8_ena gpi7_deb_e na gpi7_irq_en a 0 gpi7_ena 1000_0000_0000_0000 23 17 gpio_pol 0 0 0 irq_inv tempok_po l micshrt_po l micdet_pol pll_lck_po l 0000_1000_0000_0000 24 18 left line input 1&2 volume 0 0 0 0 0 0 0 ipvu[0] li12mute li12zc 0 0000_000p_1000_1011 25 19 left line input 3&4 volume 0 0 0 0 0 0 0 ipvu[1] li34mute li34zc 0 0000_000p_1000_1011 26 1a right line input 1&2 volume 0 0 0 0 0 0 0 ipvu[2] ri12mute ri12zc 0 0000_000p_1000_1011 27 1b right line input 3&4 volume 0 0 0 0 0 0 0 ipvu[3] ri34mute ri34zc 0 0000_000p_1000_1011 281creserved 0000000p00000000 0000_000p_0000_0000 291dreserved 0000000p00000000 0000_000p_0000_0000 301ereserved 0000000001100110 0000_0000_0110_0110 311freserved 0000000000100010 0000_0000_0010_0010 rin34vol[4:0] gpio_pol[7:0] lin12vol[4:0] lin34vol[4:0] rin12vol[4:0] gpio4_sel[3:0] gpio3_sel[3:0] gpio5_sel[3:0] adc_hpf_cut[1:0] adcl_vol[7:0] adcr_vol[7:0] gpio_status[7:0] mclk_div[1:0] adc_clkdiv[2:0] adclrc_rate[10:0] opclkdiv[3:0] bclk_div[3:0] sw_reset_chip_id[15:0] vmid_mode[1:0] aif_wl[1:0] aif_fmt[1:0]
production data WM8953 w pd, january 2009, rev 4.0 83 dec addr hex addr name 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bin default 32 20 reserved 0 0 0 0 0 0 0 p 0 1 1 1 1 0 0 1 0000_000p_0111_1001 33 21 reserved 0 0 0 0 0 0 0 p 0 1 1 1 1 0 0 1 0000_000p_0111_1001 34 22 reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0000_0000_0000_0011 35 23 reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0000_0000_0000_0011 36 24 reserved 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0000_0000_0101_0101 37 25 reserved 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0000_0001_0000_0000 38 26 reserved 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 0000_0000_0111_1001 39 27 reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000_0000_0000_0000 40 28 input mixer2 0 0 0 0 0 0 0 0 lmp4 lmn3 lmp2 lmn1 rmp4 rmn3 rmp2 rmn1 0000_0000_0000_0000 41 29 input mixer3 0 0 0 0 0 0 0 l34mnb l34mnbst 0 l12mnb l12mnbst 0 0 0 0 0000_0000_0000_0000 42 2a input mixer4 0 0 0 0 0 0 0 r34mnb r34mnbst 0 r12mnb r12mnbst 0 0 0 0 0000_0000_0000_0000 43 2b input mixer5 0 0 0 0 0 0 0 0 0 0 0 0 0 0000_0000_0000_0000 44 2c input mixer6 0 0 0 0 0 0 0 0 0 0 0 0 0 0000_0000_0000_0000 45 2d reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000_0000_0000_0000 46 2e reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000_0000_0000_0000 47 2f reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000_0000_0000_0000 48 30 reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000_0000_0000_0000 49 31 reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000_0000_0000_0000 50 32 reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000_0000_0000_0000 51 33 reserved 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0000_0001_1000_0000 52 34 reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000_0000_0000_0000 53 35 reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000_0000_0000_0000 54 36 reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000_0000_0000_0000 55 37 reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000_0000_0000_0000 56 38 reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000_0000_0000_0000 57 39 anti-pop 0 0 0 0 0 0 0 0 0 0 0 0 bufioen 0 0 0 0000_0000_0000_0000 583amicbias 00000000 mcd 0 mbsel 0000_0000_0000_0000 59 3b reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000_0000_0000_0000 60 3c pll1 0 0 0 0 0 0 0 0 sdm prescale 0 0 0000_0000_0000_1000 61 3d pll2 0 0 0 0 0 0 0 0 0000_0000_0011_0001 62 3e pll3 0 0 0 0 0 0 0 0 0000_0000_0010_0110 11775access control 00000000000000 ext_access _ena 0 0000_0000_0000_0000 122 7a extended adc control adcl_adcr_ link 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 0010_0000_0000_0011 pllk2[7:0] mcdscth[1:0] mcdthr[2:0] plln[3:0] pllk1[7:0] ri2bvol[2:0] li2bvol[2:0] note: a bin default value of ?p? indicates a register field where a default value is not applicable e.g. a volume update bit.
WM8953 production data w pd, january 2009, rev 4.0 84 register bits by address register address bit label default description r0 (00h) reset / id 15:0 sw_reset_chip_ id [15:0] (rr) 8990h writing to this register resets all registers to their default state. reading from this register will indicate device family id 8990h. 15:8 00h reserved - do not change 7:5 000b reserved - do not change 4 micbias_ena (rw) 0b micbias enable 0 = off (high impedance output) 1 = on 3 0b reserved - do not change 2:1 vmid_mode [1:0] (rw) 00b vmid divider enable and select 00 = vmid disabled (for off mode) 01 = 2 x 50k ? divider (normal mode) 10 = 2 x 250k ? divider (standby mode) 11 = 2 x 5k ? divider (for fast start-up) r1 (01h) power management (1) 0 vref_ena (rw) 0b vref enable (bias for all analogue functions) 0 = vref bias disabled 1 = vref bias enabled 15 pll_ena (rw) 0b pll enable 0 = disabled 1 = enabled 14 tshut_ena (rw) 1b thermal sensor enable 0 = thermal sensor disabled 1 = thermal sensor enabled 13:12 10b reserved - do not change 11 opclk_ena (rw) 0b gpio clock output enable 0 = disabled 1 = enabled 10 0b reserved - do not change 9 ainl_ena (rw) 0b left input path enable 0 = disabled 1 = enabled 8 ainr_ena (rw) 0b right input path enable 0 = disabled 1 = enabled 7 lin34_ena (rw) 0b lin34 input pga enable 0 = disabled 1 = enabled 6 lin12_ena (rw) 0b lin12 input pga enable 0 = disabled 1 = enabled 5 rin34_ena (rw) 0b rin34 input pga enable 0 = disabled 1 = enabled 4 rin12_ena (rw) 0b rin12 input pga enable 0 = disabled 1 = enabled 3:2 00b reserved - do not change r02 (02h) power management (2) 1 adcl_ena (rw) 0b left adc enable 0 = disabled 1 = enabled
production data WM8953 w pd, january 2009, rev 4.0 85 register address bit label default description 0 adcr_ena (rw) 0b right adc enable 0 = disabled 1 = enabled r03 (03h) power management (3) 15:0 0000h reserved - do not change 15 aifadcl_src 0b left digital audio channel source 0 = left adc data is output on left channel 1 = right adc data is output on left channel 14 aifadcr_src 1b right digital audio channel source 0 = left adc data is output on right channel 1 = right adc data is output on right channel 13 aifadc_tdm 0b adc tdm enable 0 = normal adcdat operation 1 = tdm enabled on adcdat 12 aifadc_tdm_ chan 0b adcdat tdm channel select 0 = adcdat outputs data on slot 0 1 = adcdat output data on slot 1 11:9 0b reserved - do not change 8 aif_bclk_inv 0b bclk invert 0 = bclk not inverted 1 = bclk inverted right, left and i 2 s modes ? lrclk polarity 0 = normal lrclk polarity 1 = invert lrclk polarity 7 aif_lrclk_inv 0b dsp mode ? mode a/b select 0 = msb is available on 2nd bclk rising edge after lrc rising edge (mode a) 1 = msb is available on 1st bclk rising edge after lrc rising edge (mode b) 6:5 aif_wl [1:0] 10b digital audio interface word length 00 = 16 bits 01 = 20 bits 10 = 24 bits 11 = 32 bits 4:3 aif_fmt [1:0] 10b digital audio interface format 00 = right justified 01 = left justified 10 = i 2 s format 11 = dsp mode r04 (04h) audio interface (1) 2:0 0b reserved - do not change 15:8 40h reserved - do not change 7:3 00000b reserved - do not change 2 adc_comp 0b adc companding enable 0 = disabled 1 = enabled 1 adc_compmode 0b adc companding type 0 = -law 1 = a-law r05 (05h) audio interface (2) 0 0b reserved - do not change
WM8953 production data w pd, january 2009, rev 4.0 86 register address bit label default description 15 toclk_rate 0b timeout clock rate (selects clock to be used for volume update timeout and gpio input de-bounce) 0 = sysclk / 2 21 (slower response) 1 = sysclk / 2 19 (faster response) 14 toclk_ena 0b timeout clock enable (this clock is required for volume update timeout and gpio input de-bounce) 0 = disabled 1 = enabled 13 0b reserved - do not change 12:9 opclkdiv [3:0] 0000b gpio output clock divider 0000 = sysclk 0001 = sysclk / 2 0010 = sysclk / 3 0011 = sysclk / 4 0100 = sysclk / 5.5 0101 = sysclk / 6 0110 = sysclk / 8 0111 = sysclk / 12 1000 = sysclk / 16 1001 to 1111 = reserved 8:5 1110b reserved - do not change 4:1 bclk_div [3:0] 0100b bclk frequency (master mode) 0000 = sysclk 0001 = sysclk / 1.5 0010 = sysclk / 2 0011 = sysclk / 3 0100 = sysclk / 4 0101 = sysclk / 5.5 0110 = sysclk / 6 0111 = sysclk / 8 1000 = sysclk / 11 1001 = sysclk / 12 1010 = sysclk / 16 1011 = sysclk / 22 1100 = sysclk / 24 1101 = sysclk / 32 1110 = sysclk / 44 1111 = syscl:k / 48 r06 (06h) clocking (1) 0 0b reserved - do not change 15 0b reserved - do not change 14 sysclk_src 0b sysclk source select 0 = mclk 1 = pll output r07 (07h) clocking (2) 13 clk_force 0b forces clock source selection 0 = existing sysclk source (mclk or pll output) must be active when changing to a new clock source. 1 = allows existing mclk source to be disabled before changing to a new clock source.
production data WM8953 w pd, january 2009, rev 4.0 87 register address bit label default description 12:11 mclk_div [1:0] 00b sysclk pre-divider. clock source (mclk or pll output) will be divided by this value to generate sysclk. 00 = divide sysclk by 1 01 = reserved 10 = divide sysclk by 2 11 = reserved 10 mclk_inv 0b mclk invert 0 = master clock not inverted 1 = master clock inverted 9:8 00b reserved - do not change 7:5 adc_clkdiv [2:0] 000b adc sample rate divider 000 = sysclk / 1.0 001 = sysclk / 1.5 010 = sysclk / 2.0 011 = sysclk / 3.0 100 = sysclk / 4.0 101 = sysclk / 5.5 110 = sysclk / 6.0 111= reserved 4:0 00000b reserved - do not change 15 aif_mstr 0b audio interface master mode select 0 = slave mode 1 = master mode 14:12 000b reserved - do not change 11 adclrc_dir 0b adclrc direction (forces adclrc clock to be output in slave mode) 0 = adclrc normal operation 1 = adclrc clock output enabled r08 (08h) audio interface (3) 10:0 adclrc_rate [10:0] 040h adclrc rate adclrc clock output = bclk / adclrc_rate integer (lsb = 1) valid from 8..2047 15:14 00b reserved - do not change 13 aif_tris 0b audio interface and gpio tristate 0 = audio interface and gpio pins operate normally 1 = tristate all audio interface and gpio pins 12 0b reserved - do not change r09 (09h) audio interface (4) 11:0 040h reserved - do not change 15:11 00000b reserved - do not change 10 aif_lrclkrate 0b lrclk rate 0 = normal mode (256 * fs) 1 = usb mode (272 * fs) 9:8 00b reserved - do not change r10 (0ah) lrclk rate 7:0 04h reserved - do not change r11 (0bh) 15:0 0060h reserved - do not change r12 (0ch) 15:0 0060h reserved - do not change r13 (0dh) 15:0 0000h reserved - do not change 15:9 00h reserved - do not change 8 adc_hpf_ena 1b adc digital high pass filter enable 0 = disabled 1 = enabled r14 (0eh) adc control 7 0b reserved - do not change
WM8953 production data w pd, january 2009, rev 4.0 88 register address bit label default description 6:5 adc_hpf_cut [1:0] 00b adc digital high pass filter cut-off frequency (fc) 00 = hi-fi mode (fc=4hz at fs=48khz) 01 = voice mode 1 (fc=127hz at fs=16khz) 10 = voice mode 2 (fc=130hz at fs=8khz) 11 = voice mode 3 (fc=267hz at fs=8khz) (note: fc scales with sample rate. see table 16 for cut-off frequencies at all supported sample rates) 4:2 000b reserved - do not change 1 adcl_datinv 0b left adc invert 0 = left adc output not inverted 1 = left adc output inverted 0 adcr_datinv 0b right adc invert 0 = right adc output not inverted 1 = right adc output inverted 15:9 00h reserved - do not change 8 adc_vu n/a adc volume update writing a 1 to this bit will cause left and right adc volume to be updated simultaneously r15 (0fh) left adc digital volume 7:0 adcl_vol [7:0] 1100_ 0000b (0db) left adc digital volume (see table 14 for volume range) 15:9 00h reserved - do not change 8 adc_vu n/a adc volume update writing a 1 to this bit will cause left and right adc volume to be updated simultaneously r16 (10h) right adc digital volume 7:0 adcr_vol [7:0] 1100_ 0000b (0db) right adc digital volume (see table 14 for volume range) r17 (11h) 15:0 0000h reserved - do not change 15:13 000b reserved - do not change 12 irq (ro) read only irq readback (allows polling of irq status) 11 tempok (rr) read or reset temperature ok status read- 0 = device temperature not ok 1 = device temperature ok write - 1 = reset tempok latch 10 micshrt (rr) read or reset micbias short status read- 0 = micbias ok 1 = micbias shorted write- 1 = reset micshrt latch r18 (12h) gpio control (1) 9 micdet (rr) read or reset micbias detect status micbias microphone detect readback read- 0 = no microphone detected 1 = microphone detected write- 1 = reset micdet latch
production data WM8953 w pd, january 2009, rev 4.0 89 register address bit label default description 8 pll_lck (rr) read or reset pll lock status read- 0 = pll not locked 1 = pll locked write- 1 = reset pll_lck latch 7:0 gpio_status [7:0] (rr) read or reset gpio and gpi input pin status gpio_status[7] = gpi8 pin status gpio_status[6] = gpi7 pin status gpio_status[5] = reserved gpio_status[4] = gpio5 pin status gpio_status[3] = gpio4 pin status gpio_status[2] = gpio3 pin status gpio_status[1] = reserved gpio_status[0] = reserved r19 (13h) 15:0 1000h reserved - do not change 15 gpio4_deb_ena 0b gpio4 input de-bounce 0 = disabled (not de-bounced) 1 = enabled (requires mclk input and toclk_ena=1) 14 gpio4_irq_ena 0b gpio4 irq enable 0 = disabled 1 = enabled (gpio4 input will generate irq) 13 gpio4_pu 0b gpio4 pull-up resistor enable 0 = pull-up disabled 1 = pull-up enabled (approx 150k ? ) 12 gpio4_pd 1b gpio4 pull-down resistor enable 0 = pull-down disabled 1 = pull-down enabled (approx 150k ? ) 11:8 gpio4_sel [3:0] 0000b gpio4 function select 0000 = input pin 0001 = clock output (f=sysclk/opclkdiv) 0010 = logic '0' 0011 = logic '1' 0100 = pll lock output 0101 = temperature ok output 0110 = sdout data output 0111 = irq output 1000 = mic detect 1001 = mic short circuit detect 1010 to 1111 = reserved 7 gpio3_deb_ena 0b gpio3 input de-bounce 0 = disabled (not de-bounced) 1 = enabled (requires mclk input and toclk_ena=1) 6 gpio3_irq_ena 0b gpio3 irq enable 0 = disabled 1 = enabled (gpio3 input will generate irq) 5 gpio3_pu 0b gpio3 pull-up resistor enable 0 = pull-up disabled 1 = pull-up enabled (approx 150k ? ) r20 (14h) gpio3 and gpio4 4 gpio3_pd 1b gpio3 pull-down resistor enable 0 = pull-down disabled 1 = pull-down enabled (approx 150k ? )
WM8953 production data w pd, january 2009, rev 4.0 90 register address bit label default description 3:0 gpio3_sel [3:0] 0000b gpio3 function select 0000 = input pin 0001 = clock output (f=sysclk/opclkdiv) 0010 = logic '0' 0011 = logic '1' 0100 = pll lock output 0101 = temperature ok output 0110 = sdout data output 0111 = irq output 1000 = mic detect 1001 = mic short circuit detect 1010 to 1111 = reserved 15:8 10h reserved - do not change 7 gpio5_deb_ena 0b gpio5 input de-bounce 0 = disabled (not de-bounced) 1 = enabled (requires mclk input and toclk_ena=1) 6 gpio5_irq_ena 0b gpio5 irq enable 0 = disabled 1 = enabled (gpio5 input will generate irq) 5 gpio5_pu 0b gpio5 pull-up resistor enable 0 = pull-up disabled 1 = pull-up enabled (approx 150k ? ) 4 gpio5_pd 1b gpio5 pull-down resistor enable 0 = pull-down disabled 1 = pull-down enabled (approx 150k ? ) r21 (15h) gpio5 3:0 gpio5_sel [3:0] 0000b gpio5 function select 0000 = input pin 0001 = clock output (f=sysclk/opclkdiv) 0010 = logic '0' 0011 = logic '1' 0100 = pll lock output 0101 = temperature ok output 0110 = sdout data output 0111 = irq output 1000 = mic detect 1001 = mic short circuit detect 1010 to 1111 = reserved 15 rd_3w_ena 1b 3- / 4-wire readback configuration 1 = 3-wire mode 0 = 4-wire mode, using gpio pin 14 mode_3w4w 0b 3-wire mode 0 = push 0/1 1 = open-drain 4-wire mode 0 = push 0/1 1 = wired-or 13:12 00b reserved - do not change 11 tempok_irq_ena 0b temperature sensor irq enable 0 = disabled 1 = enabled r22 (16h) gpi7 and gpi8 10 micshrt_irq_en a 0b micbias short circuit detect irq enable 0 = disabled 1 = enabled
production data WM8953 w pd, january 2009, rev 4.0 91 register address bit label default description 9 micdet_irq_ena 0b micbias current detect irq enable 0 = disabled 1 = enabled 8 pll_lck_irq_ena 0b pll lock irq enable 0 = disabled 1 = enabled 7 gpi8_deb_ena 0b gpi8 input de-bounce 0 = disabled (not de-bounced) 1 = enabled (requires mclk input and toclk_ena=1) 6 gpi8_irq_ena 0b gpi8 irq enable 0 = disabled 1 = enabled (gpi8 input will generate irq) 5 0b reserved - do not change 4 gpi8_ena 0b gpi8 input pin enable 0 = rin3/gpi8 pin disabled as gpi8 input 1 = rin3/gpi8 pin enabled as gpi8 input 3 gpi7_deb_ena 0b gpi7 input de-bounce 0 = disabled (not de-bounced) 1 = enabled (requires mclk input and toclk_ena=1) 2 gpi7_irq_ena 0b gpi7 irq enable 0 = disabled 1 = enabled (gpi7 input will generate irq) 1 0b reserved - do not change 0 gpi7_ena 0b gpi7 input pin enable 0 = lin3/gpi7 pin disabled as gpi7 input 1 = lin3/gpi7 pin enabled as gpi7 input 15:13 0000b reserved - do not change 12 irq_inv (rw) 0b irq invert 0 = irq output active high 1 = irq output active low 11 tempok_pol (rw) 1b temperature sensor polarity 0 = non-inverted 1 = inverted 10 micshrt_pol (rw) 0b micbias short circuit detect polarity 0 = non-inverted 1 = inverted 9 micdet_pol (rw) 0b micbias current detect polarity 0 = non-inverted 1 = inverted 8 pll_lck_pol (rw) 0b pll lock polarity 0 = non-inverted 1 = inverted r23 (17h) gpio control (2) 7:0 gpio_pol[7:0] (rw) 00h gpion input polarity 0 = non-inverted 1 = inverted gpio_pol[7]: gpi8 polarity gpio_pol[6]: gpi7 polarity gpio_pol[5]: reserved gpio_pol[4]: gpio5 polarity gpio_pol[3]: gpio4 polarity gpio_pol[2]: gpio3 polarity gpio_pol[1]: reserved gpio_pol[0]: reserved r24 (18h) 15:9 00h reserved - do not change
WM8953 production data w pd, january 2009, rev 4.0 92 register address bit label default description 8 ipvu[0] n/a input pga volume update writing a 1 to this bit will cause all input pga volumes to be updated simultaneously (lin12, lin34, rin12 and rin34) 7 li12mute 1b lin12 pga mute 0 = disable mute 1 = enable mute 6 li12zc 0b lin12 pga zero cross detector 0 = change gain immediately 1 = change gain on zero cross only 5 0b reserved - do not change lin12 input pga volume 4:0 lin12vol [4:0] 01011b lin12 volume (see table 8 for pga volume range) 15:9 00h reserved - do not change 8 ipvu[1] n/a input pga volume update writing a 1 to this bit will cause all input pga volumes to be updated simultaneously (lin12, lin34, rin12 and rin34) 7 li34mute 1b lin34 pga mute 0 = disable mute 1 = enable mute 6 li34zc 0b lin34 pga zero cross detector 0 = change gain immediately 1 = change gain on zero cross only 5 0b reserved - do not change r25 (19h) lin34 input pga volume 4:0 lin34vol [4:0] 01011b lin34 volume (see table 8 for pga volume range) 15:9 00h reserved - do not change 8 ipvu[2] n/a input pga volume update writing a 1 to this bit will cause all input pga volumes to be updated simultaneously (lin12, lin34, rin12 and rin34) 7 ri12mute 1b rin12 pga mute 0 = disable mute 1 = enable mute 6 ri12zc 0b rin12 pga zero cross detector 0 = change gain immediately 1 = change gain on zero cross only 5 0b reserved - do not change r26 (1ah) rin12 input pga volume 4:0 rin12vol [4:0] 01011b rin12 volume (see table 8 for pga volume range) 15:9 00h reserved - do not change 8 ipvu[3] n/a input pga volume update writing a 1 to this bit will cause all input pga volumes to be updated simultaneously (lin12, lin34, rin12 and rin34) 7 ri34mute 1b rin34 pga mute 0 = disable mute 1 = enable mute 6 ri34zc 0b rin34 pga zero cross detector 0 = change gain immediately 1 = change gain on zero cross only 5 0b reserved - do not change r27 (1bh) rin34 input pga volume 4:0 rin34vol [4:0] 01011b rin34 volume (see table 8 for pga volume range) r28 (1ch) 15:0 0000h reserved - do not change r29 (1dh) 15:0 0000h reserved - do not change r30 (1eh) 15:0 0066h reserved - do not change
production data WM8953 w pd, january 2009, rev 4.0 93 register address bit label default description r31 (1fh) 15:0 0022h reserved - do not change r32 (20h) 15:0 0079h reserved - do not change r33 (21h) 15:0 0079h reserved - do not change r34 (22h) 15:0 0003h reserved - do not change r35 (23h) 15:0 0003h reserved - do not change r36 (24h) 15:0 0055h reserved - do not change r37 (25h) 15:0 0100h reserved - do not change r38 (26h) 15:0 0079h reserved - do not change r39 (27h) 15:0 0000h reserved - do not change 15:8 00h reserved - do not change 7 lmp4 0b lin34 pga non-inverting input select 0 = lin4 not connected to pga 1 = lin4 connected to pga 6 lmn3 0b lin34 pga inverting input select 0 = lin3 not connected to pga 1 = lin3 connected to pga 5 lmp2 0b lin12 pga non-inverting input select 0 = lin2 not connected to pga 1 = lin2 connected to pga 4 lmn1 0b lin12 pga inverting input select 0 = lin1 not connected to pga 1 = lin1 connected to pga 3 rmp4 0b rin34 pga non-inverting input select 0 = rin4 not connected to pga 1 = rin4 connected to pga 2 rmn3 0b rin34 pga inverting input select 0 = rin3 not connected to pga 1 = rin3 connected to pga 1 rmp2 0b rin12 pga non-inverting input select 0 = rin2 not connected to pga 1 = rin2 connected to pga r40 (28h) input mixers (2) 0 rmn1 0b rin12 pga inverting input select 0 = rin1 not connected to pga 1 = rin1 connected to pga 15:9 00h reserved - do not change 8 l34mnb 0b lin34 pga output to inmixl mute 0 = mute 1 = un-mute 7 l34mnbst 0b lin34 pga output to inmixl gain 0 = 0db 1 = +30db 6 0b reserved - do not change 5 l12mnb 0b lin12 pga output to inmixl mute 0 = mute 1 = un-mute 4 l12mnbst 0b lin12 pga output to inmixl gain 0 = 0db 1 = +30db r41 (29h) input mixers (3) 3:0 0h reserved - do not change
WM8953 production data w pd, january 2009, rev 4.0 94 register address bit label default description 15:9 00h reserved - do not change 8 r34mnb 0b rin34 pga output to inmixr mute 0 = mute 1 = un-mute 7 r34mnbst 0b rin34 pga output to inmixr gain 0 = 0db 1 = +30db 6 0b reserved - do not change 5 r12mnb 0b rin12 pga output to inmixr mute 0 = mute 1 = un-mute 4 r12mnbst 0b rin12 pga output to inmixr gain 0 = 0db 1 = +30db r42 (2ah) input mixers (4) 3:0 0h reserved - do not change 15:9 00h reserved - do not change 8:6 li2bvol [2:0] 000b lin2 pin to inmixl gain and mute 000 = mute 001 = -12db 010 = -9db 011 = -6db 100 = -3db 101 = 0db 110 = +3db 111 = +6db r43 (2bh) input mixers (5) 5:0 000000b reserved - do not change 15:9 00h reserved - do not change 8:6 ri2bvol [2:0] 000b rin2 pin to inmixr gain and mute 000 = mute 001 = -12db 010 = -9db 011 = -6db 100 = -3db 101 = 0db 110 = +3db 111 = +6db r44 (2ch) input mixers (6) 5:0 000000b reserved - do not change r45 (2dh) 15:0 0000h reserved - do not change r46 (2eh) 15:0 0000h reserved - do not change r47 (2fh) 15:0 0000h reserved - do not change r48 (30h) 15:0 0000h reserved - do not change r49 (31h) 15:0 0000h reserved - do not change r50 (32h) 15:0 0000h reserved - do not change r51 (33h) 15:0 0180h reserved - do not change r52 (34h) 15:0 0000h reserved - do not change r53 (35h) 15:0 0000h reserved - do not change r54 (36h) 15:0 0000h reserved - do not change r55 (37h) 15:0 0000h reserved - do not change r56 (38h) 15:0 0000h reserved - do not change 15:7 00h reserved - do not change r57 (39h) anti-pop 6:4 000b reserved - do not change
production data WM8953 w pd, january 2009, rev 4.0 95 register address bit label default description 3 bufioen 0b enables the vgs / r current generator and the analogue input bias 0 = disabled 1 = enabled 2:0 000b reserved - do not change 15:8 00h reserved - do not change 7:6 mcdscth [1:0] 00b micbias short circuit current detect threshold 00 = 600ua 01 = 1200ua 10 = 1800ua 11 = 2400ua these values are for avdd=3.3v and scale proportionally with avdd. 5:3 mdcthr [2:0] 000b micbias current detect threshold 000 = 200ua 001 = 350ua 010 = 500ua 011 = 650ua 100 = 800ua 101 = 950ua 110 = 1100ua 111 = 1200ua these values are for avdd=3.3v and scale proportionally with avdd. 2 mcd 0b micbias current and short circuit detect enable 0 = disabled 1 = enabled 1 0b reserved - do not change r58 (3ah) microphone bias 0 mbsel 0b microphone bias voltage control 0 = 0.9 * avdd 1 = 0.65 * avdd r59 (3bh) 15:0 0000h reserved - do not change 15:8 00h reserved - do not change 7 sdm 0b enable pll integer mode 0 = integer mode 1 = fractional mode 6 prescale 0b divide mclk by 2 at pll input 0 = divide by 1 1 = divide by 2 5:4 00b reserved - do not change r60 (3ch) pll (1) 3:0 plln [3:0] 8h integer (n) part of pll frequency ratio. use values greater than 5 and less than 13. 15:8 00h reserved - do not change r61 (3dh) pll (2) 7:0 pllk [15:8] 31h fractional (k) part of pll frequency ratio (most significant bits) 15:8 00h reserved - do not change r62 (3eh) pll (2) 7:0 pllk [7:0] 26h fractional (k) part of pll frequency ratio (least significant bits) r63 (3fh) to r116 (74h) reserved 15:2 0000h reserved - do not change r117 (75h) access control 1 ext_access_ena 0b ext ended register map access 0 = disabled 1 = enabled
WM8953 production data w pd, january 2009, rev 4.0 96 register address bit label default description 0 0b reserved - do not change r118 (76h) to r121 (79h) reserved 15 adcl_adcr_link 0b 0 = adc sync disabled 1 = adc sync enabled r122 (7ah) extended adc control 14:0 2003h reserved - do not change r123 (7bh) to r127 (7fh) reserved
production data WM8953 w pd, january 2009, rev 4.0 97 digital filter characteristics parameter test conditions min typ max unit adc filter +/- 0.05db 0 0.454 fs passband -6db 0.5fs passband ripple +/- 0.05 db stopband 0.546s stopband attenuation f > 0.546 fs -60 db group delay 18/fs adc filter responses -140 -120 -100 -80 -60 -40 -20 0 20 0.00 0.25 0.50 0.75 frequency (fs) -0.1 -0.08 -0.06 -0.04 -0.02 0 0.02 0.04 0.06 0.08 0.1 0.00 0.25 frequency (fs) figure 59 adc digital filter frequency response figure 60 adc digital filter ripple adc high pass filter responses ma gnitude( db) 1 2.6923 7.2484 19.515 52.54 141.45 380.83 1.0253k 2.7605k 7.432k 20.009k -11.736 -10.562 -9.3883 -8.2145 -7.0407 -5.8669 -4.6931 -3.5193 -2.3455 -1.1717 2.1246m hpf_response.res magnitude(db) hpf_response2.res magnitude(db) hpf_response2.res#1 magnitude(db) 2 5.0248 12.624 31.716 79.683 200. 19 502.96 1.2636k 3.1747k 7.9761k 20.039k -83.352 -75.017 -66.682 -58.347 -50.012 -41.677 -33.342 -25.007 -16.672 -8.3373 -2.3338m figure 61 adc digital high pass filter frequency response (48khz, hi-fi mode, adc_hpf_cut[1:0]=00) figure 62 adc digital high pass filter ripple (48khz, voice mode, adc_hpf_cut=01, 10 and 11)
WM8953 production data w pd, january 2009, rev 4.0 98 applications information recommended external components notes: 1. wolfson recommend using a single, common ground reference. where this is not possible care should be taken to optimise split ground configuration for audio performance. 2. supply decoupling capacitors on dcvdd, dbvdd and avdd should be positioned as close to the WM8953 as possible. values indica ted are minimum requirements. 3. capacitor types should be carefully chosen. capacitors with very low esr are recommended for optimum performance. 4. the 2k2 micbias resistors on each of the mic inputs are typical values and will be suitable for many electret type microphon es. however, it is recommended that engineers refer to individual microphone specifications prior to finalising the value of this c omponent. WM8953 avdd dcvdd dbvdd mode sdin sclk csb/addr mclk bclk adclrc adcdat gpio5 gpio4 gpio3 lin1 lin4 lin3/gpi7 lin2 rin1 rin4 rin3/gpi8 rin2 agnd dgnd micbias vmid 1 f 1 f 4.7 f control interface (2, 3 or 4-wire via gpio) audio interface gpio 4.7 f 0.1 f 0.1 f dvdd avdd 1 f 1 f 1 f 1 f 1 f 1 f micbias micbias 2k2 2k2 headset mic handset mic agnd 4.7 f line inputs line inputs
production data WM8953 w pd, january 2009, rev 4.0 99 package dimensions dm049.c b: 42 ball w-csp package 3.226 x 3.440 x 0.7mm body, 0.50 mm ball pitch a1 corner top view e z 0.10 2 x d 5 4 detail 2 detail 2 a a2 2 z 0.10 2 x a1 z bbb z 1 solder ball e1 a d1 detail 1 d c b g f e e e bottom view 1 65432 6 f f g h notes: 1. primary datum -z- and seating plane are defined by the spherical crowns of the solder balls. 2. this dimension includes stand-off height ?a1? and backside coating. 3. a1 corner is identified by ink/laser mark on top package. 4. bilateral tolerance zone is applied to each side of the package body. 5. ?e? represents the basic solder ball grid pitch. 6. this drawing is subject to change without notice. 7. follows jedec design guide mo-211-c. a1 0.225 d d1 e e1 e 2.500 bsc 3.440 bsc 0.060 bsc 3.00 bsc 0.50 bsc 3.226 bsc dimensions (mm) symbols min nom max note a 0.7 a2 0.355 0.380 0.405 5 f 0.785 0.615 0.250 0.275 g 0.070 0.035 0.105 h 0.315 bsc
WM8953 production data w pd, january 2009, rev 4.0 100 important notice wolfson microelectronics plc (?wolfson?) products and services are sold subject to wolfson?s terms and conditions of sale, delivery and payment supplied at the time of order acknowledgement. wolfson warrants performance of its products to the specifications in effect at the date of shipment. wolfson reserves the right to make changes to its products and specifications or to discontinue any product or service without notice. customers should therefore obtain the latest version of relevant information from wolfson to verify that the information is current. testing and other quality control techniques are utilised to the extent wolfson deems necessary to support its warranty. specific testing of all parameters of each device is not necessarily performed unless required by law or regulation. in order to minimise risks associated with customer applications, the customer must use adequate design and operating safeguards to minimise inherent or procedural hazards. wolfson is not liable for applications assistance or customer product design. the customer is solely responsible for its selection and use of wolfson products. wolfson is not liable for such selection or use nor for use of any circuitry other than circuitry entirely embodied in a wolfson product. wolfson?s products are not intended for use in life support systems, appliances, nuclear systems or systems where malfunction can reasonably be expected to result in personal injury, death or severe property or environmental damage. any use of products by the customer for such purposes is at the customer?s own risk. wolfson does not grant any licence (express or implied) under any patent right, copyright, mask work right or other intellectual property right of wolfson covering or relating to any combination, machine, or process in which its products or services might be or are used. any provision or publication of any third party?s products or services does not constitute wolfson?s approval, licence, warranty or endorsement thereof. any third party trade marks contained in this document belong to the respective third party owner. reproduction of information from wolfson datasheets is permissible only if reproduction is without alteration and is accompanied by all associated copyright, proprietary and other notices (including this notice) and conditions. wolfson is not liable for any unauthorised alteration of such information or for any reliance placed thereon. any representations made, warranties given, and/or liabilities accepted by any person which differ from those contained in this datasheet or in wolfson?s standard terms and conditions of sale, delivery and payment are made, given and/or accepted at that person?s own risk. wolfson is not liable for any such representations, warranties or liabilities or for any reliance placed thereon by any person. address: wolfson microelectronics plc 26 westfield road edinburgh eh11 2qb united kingdom tel :: +44 (0)131 272 7000 fax :: +44 (0)131 272 7001 email :: sales@wolfsonmicro.com

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